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PM8316
TM
TEMUX-84
TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER
DATASHEET
PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 5:OCTOBER 2001
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Legal Information
Copyright
(c) 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. PMC-1991437 (P5), ref PMC-1991191 (P6)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
Trademarks
TEMUX, SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc.
Patents
The technology discussed is protected by one or more of the following Patents: U.S. Patent No. 5,640,398 Canadian patent 2,161,921 Relevant patent applications and other patents may also exist.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Revision History
Issue No. 1 2 3 4 5 Issue Date Oct 27, 1999 Jan 24, 2000 Oct 19, 2000 May 4, 2001 Oct 22, 2001 Originator Larry Kennedy Larry Kennedy Jillian Mallory Tracey Martinsen Tracey Martinsen Details of Change Original Document. Advance version. Upgrade document from Preview to Advance Preliminary version released in conjunction with Rev. A tapeout Datasheet updated to reflect Issue 5 of PMC-1991191. Datasheet updated to reflect Issue 6 of PMC-1991191. Go to the sections noted below to see the marked corrections in the text. Change to Section 1: HDLC interface with 127 bytes of buffering for terminating the facility data link. Change to Section 1: Seamlessly interfaces with 77.76 MHz Drop and 77.76 MHz Add buses. New: Figure 1 Fractional DS3 Application New: Figure 2 TEMUX-84 Block Diagram Change to Section 6: In this configuration the T1 and E1 transmit framers are disabled and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers for performance monitoring purposes, which include error event accumulation, alarm monitoring and HDLC termination. Changes in pin table: Framer Recovered Clock (RSCLK[3:1])... When a DS3 is demapped from SONET/SDH (i.e. LINEOPT_SPEx = 01), RSCLK is a gapped version of CLK52M. The Ingress Flexible Bandwidth Enables (IFBWEN[3:1])... The IFBWEN[3:1] inputs are constrained such that the maximum data rate of each of IFBWDAT[3:1] is less than 48.96 Mbit/s. System Reference Clock (SREFCLK)... This clock must be phase locked to LREFCLK and can be external connected to LREFCLK. When passing transparent virtual tributaries between the telecom bus and the SBI bus, SREFCLK must be the same frequency as LREFCLK (i.e. S77 = L77). Change in second note to pin table: The outputs TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, LAOE/LATPL, RECVCLK1, RECVCLK2, RECVCLK3, CASID[21:1], CCSID, TS0ID, TDO and INTB have 4 mA drive capability... The bidirectional SBI signal SDC1FP has 8mA drive capability. MVID[21:1] have 8mA drive capability.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Changes to section 9.1 New: Section 9.2 Change to Section 9.3: For ESF, out-of-frame declaration is based strictly on Frame Alignment Signal (F1-F6) bit errors; a new frame search is never initiated upon excessive CRC-6 errors. Change to Section 9.6: Received data is placed into a 127-byte FIFO buffer. Changes to Section 9.14 Changes to Section 9.21: Add E3 New: Table 1 Path Signal Label Mismatch State New: Section 19.37.1 Change to end of Section 9.40 The CCS H-MVIP interface, CCSID[1:3], is not multiplexed with any other pins. The CCSID[1:3] outputs is always available provided CMV8MCLK, CMVFPB and CMVFPC are active. Change to Section 9.43: SPE (48.96 Mbit/s). New: Section 9.43.1 Burst Lengths on Ingress Flexible Bandwidth Port Change to Section 9.44: The TEMUX-84 identification code is 183160CD hexadecimal. Changes to Table 2 Register Memory Map: 0x0157 0x01E9 0x01EA 0x0F20 + 0x40*N SIGX Configuration INSBI T1 Thresholds Register INSBI E1 Thresholds Register RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIM Interrupt
Change to bullet in Section 12.2.1: The SAC1FP pulse must be 3n +/ 1 (where n = 0,1,2...) SREFCLK cycles before the LAC1 pulse. Change to Section 12.2.2: When TVTs are supported an additional constraint exists between SAC1FP and LAC1. Table 16 gives the permissible combinations. New: Table 3 TVT Constraints for 77.76MHz Change to Section 12.2.3: TVTs are not supported for this bus configuration. Change to Section 12.3.2: The T1 framer will determine frame alignment within 13ms Change to Step 10 in 12.8: If PBS[2:0] = 1XX, discard the data byte
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
read in step 5, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. Changes to Section 12.14 and Fig 27: Add E3 Change to text just before Table 32: The signaling contained within the robbed bit positions of the DS0s will also have an arbitrary alignment relative to the P1P0 bits. Change to text just after Table 38: When carrying framed E3, only the ITU-T Rec. G.751 format is supported. Unframed E3 is carried clear channel. Changes to Table 39 E3 Frame Stuffing Format Just before Figure 61: The LAC1J1V1 signal is high when the LAPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The LAV5 signal pulses high to mark the V5 bytes of each tributary. LATPL, multiplexed with LAOE shown separately in [x-ref], indicates valid tributary payload when high. During the V3 location LATPL indicates a negative pointer justification when high and during the byte after the V3 location LATPL low indicates a positive pointer justification. The three STS-1 SPEs have an alignment determined by the SONET/SDH Transmit Pointer Configuration registers. A pointer of 522 decimal is illustrated in [x-ref]. Changes to Table 51 Changes to Table 54 Changes to Table 56 Changes to Table 58 Changes to Table 62
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
CONTENTS LEGAL INFORMATION .......................................................................................II REVISION HISTORY..........................................................................................III 1 2 3 4 5 FEATURES...............................................................................................1 APPLICATIONS ......................................................................................16 REFERENCES .......................................................................................17 APPLICATION EXAMPLES ....................................................................21 BLOCK DIAGRAM..................................................................................25 5.1 5.2 5.3 5.4 6 7 8 9 TOP LEVEL BLOCK DIAGRAM ...................................................25 M13 MULTIPLEXER MODE BLOCK DIAGRAM ..........................26 VT/TU MAPPER ONLY MODE BLOCK DIAGRAM......................27 DS3/E3 FRAMER ONLY BLOCK DIAGRAM ...............................28
DESCRIPTION .......................................................................................29 PIN DIAGRAM ........................................................................................34 PIN DESCRIPTION ................................................................................35 FUNCTIONAL DESCRIPTION................................................................76 9.1 9.2 9.3 9.4 9.5 9.6 TRANSPARENT VIRTUAL TRIBUTARIES...................................76 TRANSMULTIPLEXING ...............................................................77 T1 FRAMING ...............................................................................77 E1 FRAMING ...............................................................................80 T1/E1 PERFORMANCE MONITORING ......................................87 T1/E1 HDLC RECEIVER .............................................................87
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 9.27
T1/E1 ELASTIC STORE (ELST) ..................................................88 T1/E1 SIGNALING EXTRACTION ...............................................89 T1/E1 RECEIVE PER-CHANNEL CONTROL..............................89 T1 TRANSMITTER ......................................................................90 E1 TRANSMITTER ......................................................................91 T1/E1 HDLC TRANSMITTERS ....................................................92 T1/E1 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATORS ...........................................................................93 T1/E1 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION (PRBS)...........................................................98 DS3 FRAMER (DS3-FRMR) ........................................................99 DS3 BIT ORIENTED CODE DETECTION .................................101 DS3/E3 HDLC RECEIVER (RDLC)............................................101 DS3/E3 PERFORMANCE MONITOR ACCUMULATOR (DS3/E3-PMON) ........................................................................102 DS3 TRANSMITTER (DS3-TRAN) ............................................103 DS3/E3 HDLC TRANSMITTERS ...............................................105 DS3/E3 PSEUDO RANDOM PATTERN GENERATION AND DETECTION (PRGD).................................................................106 M23 MULTIPLEXER (MX23)......................................................106 DS2 FRAMER (DS2 FRMR) ......................................................107 M12 MULTIPLEXER (MX12)......................................................108 E3 FRAMER............................................................................... 110 E3 TRANSMITTER .................................................................... 112 E3 TRAIL TRACE BUFFER ....................................................... 114
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9.28 9.29 9.30 9.31 9.32 9.33 9.34 9.35 9.36 9.37 9.38 9.39 9.40 9.41 9.42 9.43 9.44 9.45 10 11
TRIBUTARY PAYLOAD PROCESSOR (VTPP) ......................... 114 RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR (RTOP) ................................................................................................... 116 RECEIVE TRIBUTARY TRACE BUFFER (RTTB)...................... 118 RECEIVE TRIBUTARY BIT ASYNCHRONOUS DEMAPPER (RTDM) ...................................................................................... 119 RECEIVE TRIBUTARY BYTE SYNCHRONOUS DEMAPPER ..122 DS3 MAPPER DROP SIDE (D3MD)..........................................123 TRANSMIT TRIBUTARY PATH OVERHEAD PROCESSOR (TTOP) .......................................................................................126 TRANSMIT REMOTE ALARM PROCESSOR (TRAP)...............127 TRANSMIT TRIBUTARY BIT ASYNCHRONOUS MAPPER (TTMP).......................................................................................128 TRANSMIT TRIBUTARY BYTE SYNCHRONOUS MAPPER ....129 DS3 MAPPER ADD SIDE (D3MA) .............................................130 EGRESS H-MVIP SYSTEM INTERFACE ..................................131 INGRESS SYSTEM H-MVIP INTERFACE.................................133 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI) ......................................................................................134 INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI)136 FLEXIBLE BANDWIDTH PORTS ..............................................137 JTAG TEST ACCESS PORT......................................................138 MICROPROCESSOR INTERFACE ...........................................139
NORMAL MODE REGISTER DESCRIPTION ......................................166 TEST FEATURES DESCRIPTION .......................................................167
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
11.1 12
JTAG TEST PORT .....................................................................170
OPERATION.........................................................................................177 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 TRIBUTARY INDEXING.............................................................177 CLOCK AND FRAME SYNCHRONIZATION CONSTRAINTS ...179 SLCO96 .....................................................................................182 DS3 FRAME FORMAT...............................................................184 SERVICING INTERRUPTS........................................................186 USING THE PERFORMANCE MONITORING FEATURES.......186 USING THE INTERNAL DS3 OR E3 HDLC TRANSMITTER ....190 USING THE INTERNAL DS3 OR E3 DATA LINK RECEIVER ...194 USING THE INTERNAL T1/E1 DATA LINK RECEIVER.............198
12.10 USING THE INTERNAL T1/E1 DATA LINK TRANSMITTER......201 12.11 USING THE TIME-SLICED T1/E1 TRANSCEIVERS.................203 12.12 T1 AUTOMATIC PERFORMANCE REPORT FORMAT .............203 12.13 T1/E1 FRAMER LOOPBACK MODES.......................................205 12.14 DS3 AND E3 LOOPBACK MODES............................................207 12.15 TELECOM BUS MAPPER/DEMAPPER LOOPBACK MODES..210 12.16 SBI BUS DATA FORMATS......................................................... 211 12.17 H-MVIP DATA FORMAT .............................................................232 12.18 JTAG SUPPORT........................................................................238 13 FUNCTIONAL TIMING..........................................................................246 13.1 13.2 DS3 LINE SIDE INTERFACE TIMING .......................................246 DS3 AND E3 SYSTEM SIDE INTERFACE TIMING...................250
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 15 16 17 18 19
TELECOM DROP BUS INTERFACE TIMING............................254 TELECOM ADD BUS INTERFACE TIMING...............................257 SONET/SDH SERIAL ALARM PORT TIMING ...........................260 SBI DROP BUS INTERFACE TIMING .......................................261 SBI ADD BUS INTERFACE TIMING ..........................................262 EGRESS H-MVIP LINK TIMING ................................................263 INGRESS H-MVIP LINK TIMING ...............................................264
ABSOLUTE MAXIMUM RATINGS........................................................265 D.C. CHARACTERISTICS....................................................................266 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......269 TEMUX-84 TIMING CHARACTERISTICS............................................273 ORDERING AND THERMAL INFORMATION ......................................297 MECHANICAL INFORMATION.............................................................298
LIST OF FIGURES FIGURE 1 ANY-SERVICE-ANY-PORT APPLICATION ....................................21 FIGURE 2 HIGH DENSITY FRAME RELAY APPLICATION............................22 FIGURE 3 FRACTIONAL DS3 APPLICATION ................................................23 FIGURE 4 TEMUX-84 BLOCK DIAGRAM.......................................................25 FIGURE 5 M13 MULTIPLEXER BLOCK DIAGRAM........................................26 FIGURE 6 VT/TU MAPPER BLOCK DIAGRAM..............................................27 FIGURE 7 DS3/E3 FRAMER ONLY MODE BLOCK DIAGRAM......................28 FIGURE 8 PIN DIAGRAM ...............................................................................34
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
FIGURE 9 CRC MULTIFRAME ALIGNMENT ALGORITHM............................83 FIGURE 10 JITTER TOLERANCE T1 MODES ...............................................94 FIGURE 11 JITTER TOLERANCE E1 MODES ...............................................95 FIGURE 12 JITTER TRANSFER T1 MODES .................................................96 FIGURE 13 JITTER TRANSFER E1 MODES .................................................97 FIGURE 14 EGRESS CLOCK SLAVE: H-MVIP ............................................132 FIGURE 15 INGRESS CLOCK SLAVE: H-MVIP...........................................133 FIGURE 16 INSERT SBI ...............................................................................136 FIGURE 17 DS3 FRAME STRUCTURE .......................................................184 FIGURE 18 FER COUNT VS. BER (E1 MODE)............................................188 FIGURE 19 CRCE COUNT VS. BER (E1 MODE).........................................189 FIGURE 20 FER COUNT VS. BER (T1 ESF MODE) ....................................189 FIGURE 21 CRCE COUNT VS. BER (T1 ESF MODE) .................................190 FIGURE 22 CRCE COUNT VS. BER (T1 SF MODE) ...................................190 FIGURE 23 TYPICAL DATA FRAME .............................................................197 FIGURE 24 EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ........197 FIGURE 25 T1/E1 LINE LOOPBACK ............................................................206 FIGURE 26 T1/E1 DIAGNOSTIC DIGITAL LOOPBACK ...............................207 FIGURE 27 DS3/E3 DIAGNOSTIC LOOPBACK DIAGRAM .........................208 FIGURE 28 DS3 AND E3 LINE LOOPBACK DIAGRAM ...............................209 FIGURE 29 DS2 LOOPBACK DIAGRAM......................................................209 FIGURE 30 TELECOM DIAGNOSTIC LOOPBACK DIAGRAM ....................210 FIGURE 31 TELECOM LINE LOOPBACK DIAGRAM .................................. 211
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
FIGURE 32 BOUNDARY SCAN ARCHITECTURE .......................................238 FIGURE 33 TAP CONTROLLER FINITE STATE MACHINE .........................240 FIGURE 34 INPUT OBSERVATION CELL (IN_CELL) ..................................243 FIGURE 35 OUTPUT CELL (OUT_CELL).....................................................244 FIGURE 36 BIDIRECTIONAL CELL (IO_CELL)............................................245 FIGURE 37 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS.................................................................................245 FIGURE 38 RECEIVE BIPOLAR DS3 STREAM ...........................................246 FIGURE 39 RECEIVE UNIPOLAR DS3 STREAM ........................................246 FIGURE 40 RECEIVE BIPOLAR E3 STREAM..............................................247 FIGURE 41 RECEIVE UNIPOLAR E3 STREAM...........................................247 FIGURE 42 TRANSMIT BIPOLAR DS3 STREAM ........................................248 FIGURE 43 TRANSMIT UNIPOLAR DS3 STREAM......................................248 FIGURE 44 TRANSMIT BIPOLAR E3 STREAM ...........................................249 FIGURE 45 TRANSMIT UNIPOLAR E3 STREAM ........................................249 FIGURE 46 FRAMER MODE DS3 TRANSMIT INPUT STREAM..................250 FIGURE 47 FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH TGAPCLK..............................................................................................250 FIGURE 48 FRAMER MODE DS3 RECEIVE OUTPUT STREAM ................251 FIGURE 49 FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH RGAPCLK .............................................................................................251 FIGURE 50 FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM..........251 FIGURE 51 FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM WITH TGAPCLK..............................................................................................252 FIGURE 52 FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM ........252
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
FIGURE 53 FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK .............................................................................................252 FIGURE 54 FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM..........253 FIGURE 55 FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM WITH TGAPCLK..............................................................................................253 FIGURE 56 FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM ........254 FIGURE 57 FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK .............................................................................................254 FIGURE 58 TELECOM DROP BUS TIMING - STS-1 SPES / AU3 VCS.......255 FIGURE 59 TELECOM DROP BUS TIMING - LOCKED STS-1 SPES / AU3 VCS.............................................................................................256 FIGURE 60 TELECOM DROP BUS TIMING - AU4 VC.................................257 FIGURE 61 TELECOM ADD BUS TIMING - LOCKED STS-1 SPES / AU3 VCS.............................................................................................258 FIGURE 62 TELECOM ADD BUS TIMING - LOCKED AU4 VC CASE .........259 FIGURE 63 REMOTE SERIAL ALARM PORT TIMING.................................261 FIGURE 64 SBI DROP BUS T1/E1 FUNCTIONAL TIMING ..........................261 FIGURE 65 SBI DROP BUS DS3/E3 FUNCTIONAL TIMING .......................262 FIGURE 66 SBI ADD BUS JUSTIFICATION REQUEST FUNCTIONAL TIMING ....................................................................................262 FIGURE 67 EGRESS 8.192 MBIT/S H-MVIP LINK TIMING .........................264 FIGURE 68 INGRESS 8.192 MBIT/S H-MVIP LINK TIMING ........................264 FIGURE 69 DS3/E3 TRANSMIT INTERFACE TIMING .................................275 FIGURE 70 DS3/E3 RECEIVE INTERFACE TIMING ...................................277 FIGURE 71 LINE SIDE TELECOM BUS INPUT TIMING ..............................280 FIGURE 72 TELECOM BUS OUTPUT TIMING ............................................282
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
FIGURE 73 TELECOM BUS TRISTATE OUTPUT TIMING...........................282 FIGURE 74 SBI ADD BUS TIMING ...............................................................284 FIGURE 75 SBI DROP BUS TIMING ............................................................286 FIGURE 76 SBI DROP BUS COLLISION AVOIDANCE TIMING...................286 FIGURE 77 EGRESS FLEXIBLE BANDWIDTH PORT TIMING....................287 FIGURE 78 INGRESS FLEXIBLE BANDWIDTH PORT TIMING ..................288 FIGURE 79 H-MVIP EGRESS DATA & FRAME PULSE TIMING..................290 FIGURE 80 H-MVIP INGRESS DATA TIMING ..............................................291 FIGURE 81 XCLK INPUT TIMING.................................................................292 FIGURE 82 TRANSMIT LINE INTERFACE TIMING .....................................293 FIGURE 83 REMOTE SERIAL ALARM PORT TIMING.................................294 FIGURE 84 JTAG PORT INTERFACE TIMING.............................................296 FIGURE 85 324 PIN PBGA 23X23MM BODY ...............................................298
LIST OF TABLES TABLE 1 E1 FRAMER FRAMING STATES .....................................................84 TABLE 2 PATH SIGNAL LABEL MISMATCH STATE..................................... 118 TABLE 3 ASYNCHRONOUS T1 TRIBUTARY MAPPING..............................120 TABLE 4 ASYNCHRONOUS E1 TRIBUTARY MAPPING .............................121 TABLE 5 ASYNCHRONOUS DS3 MAPPING TO STS-1 (STM-0/AU3).........123 TABLE 6 DS3 AIS FORMAT ..........................................................................124 TABLE 7 DS3 DESYNCHRONIZER CLOCK GAPPING ALGORITHM .........126 TABLE 8 DS3 SYNCHRONIZER BIT STUFFING ALGORITHM ...................131
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
TABLE 9 REGISTER MEMORY MAP ...........................................................139 TABLE 10 INSTRUCTION REGISTER..........................................................170 TABLE 11 IDENTIFICATION REGISTER ......................................................170 TABLE 12 BOUNDARY SCAN REGISTER ...................................................171 TABLE 13 INDEXING FOR 1.544 MBIT/S TRIBUTARIES ............................178 TABLE 14 INDEXING FOR 2.048 MBIT/S TRIBUTARIES ............................179 TABLE 15 77.76 SBI AND TELECOM BUS ALIGNMENT OPTIONS ............180 TABLE 16 TVT CONSTRAINTS FOR 77.76MHZ ..........................................180 TABLE 17 19.44 MHZ SBI TO 77.76 MHZ TELECOM TO BUS ALIGNMENT OPTIONS...................................................................................181 TABLE 18 77.76 MHZ SBI TO 19.44 MHZ TELECOM TO BUS ALIGNMENT OPTIONS...................................................................................181 TABLE 19 PMON COUNTER SATURATION LIMITS (E1 MODE).................187 TABLE 20 PMON COUNTER SATURATION LIMITS (T1 MODE).................187 TABLE 21 PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS ............................................................................................203 TABLE 22 PERFORMANCE REPORT MESSAGE STRUCTURE NOTES...204 TABLE 23 PERFORMANCE REPORT MESSAGE CONTENTS...................205 TABLE 24 STRUCTURE FOR CARRYING MULTIPLEXED LINKS ..............213 TABLE 25 T1/TVT1.5 TRIBUTARY COLUMN NUMBERING.........................213 TABLE 26 E1/TVT2 TRIBUTARY COLUMN NUMBERING ...........................214 TABLE 27 SBI T1/E1 LINK RATE INFORMATION ........................................217 TABLE 28 SBI T1/E1 CLOCK RATE ENCODING .........................................217 TABLE 29 DS3 LINK RATE INFORMATION..................................................218 TABLE 30 DS3 CLOCK RATE ENCODING...................................................218
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
TABLE 31 T1 FRAMING FORMAT ................................................................219 TABLE 32 T1 CHANNEL ASSOCIATED SIGNALING BITS ..........................220 TABLE 33 E1 FRAMING FORMAT................................................................222 TABLE 34 E1 CHANNEL ASSOCIATED SIGNALING BITS ..........................223 TABLE 35 DS3 FRAMING FORMAT .............................................................224 TABLE 36 DS3 BLOCK FORMAT..................................................................225 TABLE 37 DS3 MULTI-FRAME STUFFING FORMAT...................................225 TABLE 38 E3 FRAMING FORMAT................................................................226 TABLE 39 E3 FRAME STUFFING FORMAT.................................................227 TABLE 40 TRANSPARENT VT1.5/TU11 FORMAT .......................................228 TABLE 41 TRANSPARENT VT2/TU12 FORMAT ..........................................231 TABLE 42 DATA AND CAS T1 H-MVIP FORMAT..........................................233 TABLE 43 DATA AND CAS E1 H-MVIP FORMAT .........................................234 TABLE 44 CCS AND TS0 H-MVIP FORMAT.................................................235 TABLE 45 ABSOLUTE MAXIMUM RATINGS................................................265 TABLE 46 D.C. CHARACTERISTICS............................................................266 TABLE 47 MICROPROCESSOR INTERFACE READ ACCESS ...................269 TABLE 48 MICROPROCESSOR INTERFACE WRITE ACCESS..................271 TABLE 49 RSTB TIMING ..............................................................................273 TABLE 50 DS3/E3 TRANSMIT INTERFACE TIMING ...................................273 TABLE 51 DS3/E3 RECEIVE INTERFACE TIMING ......................................277 TABLE 52 LINE SIDE TELECOM BUS INPUT TIMING - 19.44 MHZ (FIGURE 74).................................................................................279
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
TABLE 53 TELECOM BUS OUTPUT TIMING - 19.44 MHZ (FIGURE 72 AND FIGURE 73)........................................................................281 TABLE 54 TELECOM BUS OUTPUT TIMING - 77.76 MHZ (FIGURE 72 AND FIGURE 73)........................................................................281 TABLE 55 SBI ADD BUS TIMING - 19.44 MHZ (FIGURE 74) ......................283 TABLE 56 SBI ADD BUS TIMING - 77.76 MHZ (FIGURE 74) ......................284 TABLE 57 SBI DROP BUS TIMING - 19.44 MHZ (FIGURE 72 AND FIGURE 75).....................................................................................................285 TABLE 58 SBI DROP BUS TIMING - 77.76 MHZ (FIGURE 75 TO FIGURE 76).....................................................................................................285 TABLE 59 EGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE 77)....................................................................................................287 TABLE 60 INGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE 78)....................................................................................................288 TABLE 61 H-MVIP EGRESS TIMING (FIGURE 79)......................................289 TABLE 62 H-MVIP INGRESS TIMING (FIGURE 80).....................................290 TABLE 63 XCLK INPUT (FIGURE 81)...........................................................292 TABLE 64 TRANSMIT LINE INTERFACE TIMING (FIGURE 82) ..................292 TABLE 65 REMOTE SERIAL ALARM PORT TIMING ...................................293 TABLE 66 JTAG PORT INTERFACE.............................................................295 TABLE 67 ORDERING INFORMATION ........................................................297 TABLE 68 THERMAL INFORMATION - THETA JA VS. AIRFLOW ...............297
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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FEATURES Integrates 84 T1/E1 framers, three SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mappers, three full featured M13 multiplexers with DS3 framers, three E3 framers, and three SONET/SDH DS3 mappers in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams. Each SPE/DS3 independently programmable to allow the following modes of operation: Eight T1 modes of operation: Up to 84 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries into three STS-1 SPEs or TU-11 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4. Up to 84 T1 streams mapped as byte synchronous VT1.5 virtual tributaries into three STS-1 SPEs or TU-11 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4. Three STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mappers with ingress or egress per tributary link monitoring. Up to 84 T1 streams M13 multiplexed into three serial DS3 streams. Up to 84 T1 streams M13 multiplexed into three DS3s, the DS3s are asynchronously mapped into three STS-1/STM-0 SPEs. DS3 M13 Multiplexer with ingress or egress per link monitoring. Up to 84 DS3 multiplexed T1 streams are mapped as bit asynchronous VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing ("transmux") function between DS3 and SONET/SDH. Up to 63 T1 streams mapped as bit asynchronous TU-12 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4. Four E1 modes of operation: Up to 63 E1 streams mapped as bit asynchronous VT2 virtual tributaries into three STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
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PROPRIETARY AND CONFIDENTIAL
1
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Up to 63 E1 streams mapped as byte synchronous VT2 virtual tributaries into three STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4. Three STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mappers with ingress or egress per tributary link monitoring. Up to 63 E1 streams multiplexed into three DS3s following the ITU-T G.747 recommendation. Two unchannelized DS3 modes of operation: Standalone unchannelized DS3 framer mode for access to the entire DS3 payload. Up to three DS3 streams are mapped bit asynchronously into VC-3s. Standalone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload. Up to 84 VT1.5/TU11 or 63 VT2/TU12 tributaries can be passed between the line SONET/SDH bus and the SBI bus as transparent virtual tributaries with pointer processing. Supports 8 Mbit/s H-MVIP on the system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels. Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams, 63 E1 streams, 3 DS3 streams or 3 E3 streams. This interface also supports transparent virtual tributaries when used with the SONET/SDH mapper. Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to and from the SBI bus interface. Provides jitter attenuation in the T1 or E1 receive and transmit directions. Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy. Provides per link diagnostic and line loopbacks.
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PROPRIETARY AND CONFIDENTIAL
2
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Provides an on-board programmable binary sequence generator and detector for error testing at DS3 and E3 rates. Includes support for patterns recommended in ITU-T O.151. Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152. Supports the M23 and C-bit parity DS3 formats. When configured to operate as a DS3 or E3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits. DS3 or E3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed). Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU-11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3 mapper. Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Low power 1.8V/3.3V CMOS technology. All pins are 5V tolerant. 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40oC to 85oC) operation. Each one of 84 T1 receiver sections:
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Frames to DS-1 signals in SF, SLCO96 and ESF formats. Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. Provides Red, Yellow, and AIS alarm integration. Supports RAI-CI and AIS-CI alarm detection and generation. Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Provides Inband Loopback Code generation and detection. Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis. Provides an HDLC interface with 127 bytes of buffering for terminating the facility data link. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment in support of a H-MVIP interface. Provides DS-1 robbed bit signaling extraction and insertion, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis. A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 -1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 16-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1. Line side interface is either from the DS3 interface via the M13 multiplex or from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper. System side interface is either H-MVIP or SBI bus. Frames in the presence of and detects the "Japanese Yellow" alarm. Supports the alternate CRC-6 calculation for Japanese applications. Provides external access for up to three de-jittered recovered T1 clocks. Each one of 63 E1 receiver sections:
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Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications. Provides an HDLC interface with 127 bytes of buffering for terminating the national use bit data link.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233. V5.2 link indication signal detection. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction. Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16. Can be programmed to generate an interrupt on change of signaling state. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 -1, may be detected in the E1 stream in either the ingress or egress directions. The detector counts pattern errors using a 16-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire E1 or any combination of timeslots within the framed E1. Line side interface is from the SONET/SDH Drop bus via the VT2 or TU-12 demapper. System side interface is either H-MVIP or SBI bus. Provides external access for up to three de-jittered recovered E1 clocks. Each one of 84 T1 transmitter sections:
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May be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an N*8 kHz reference. Provides minimum ones density through Bell (bit 7), GTE or "jammed bit 8" zero code suppression on a per-DS0 basis.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Provides a 128 byte buffer to allow insertion of the facility data link using the host interface. Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in SF, SLCO96 and ESF formats. Provides transparency for the F-bit to support SLCO96 data link insertion. Autonomously transmits an ESF Performance Report Message each second. Provides a digital phase locked loop for generation of a low jitter transmit clock. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter. Supports the alternate ESF CRC-6 calculation for Japanese applications. A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 -1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1. Line side interface is through either DS3 Interface via the M13 multiplex or the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper. System side interface is either H-MVIP or SBI bus. Each one of 63 E1 transmitter sections:
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Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path. Transmits G.704 basic and CRC-4 multiframe formatted E1. Supports unframed mode and framing bit, CRC, or data link by-pass. Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides a digital phase locked loop for generation of a low jitter transmit clock.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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A pseudo-random sequence user selectable from 27 -1, 211 -1, 215 -1 or 220 -1, may be inserted into the E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1. Optionally inserts a datalink in the E1 national use bits. Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233 Supports transmission of the alarm indication signal (AIS) and the remote alarm indication (RAI) signal. Line side interface is through the SONET/SDH Add bus via the VT2 or TU-12 mapper. System side interface is either H-MVIP or SBI bus. Six full featured T1/E1 Pattern Generators and Detectors:
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Each generator and detector pair may be associated with any one of the 84 T1s or 63 E1s. Any sub-set of DS0s within a tributary may be selected. Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any repeating pattern up to 32 bits. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7. Each one of three SONET/SDH Tributary Path Processing Sections:
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Interfaces with a byte wide Telecom Add/Drop bus, interfacing directly with the PM5362 TUPP-PLUS and PM5342 SPECTRA-155 at 19.44 MHz. Seamlessly interfaces with 77.76 MHz Drop and 77.76 MHz Add buses. Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level tributary pointers. Optionally frames to the H4 byte in the path overhead to determine tributary multi-frame boundaries and generates change of loss-of-frame status interrupts.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Detects loss of pointer (LOP) and re-acquisition for each tributary and optionally generates interrupts. Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts Detects tributary elastic store underflow and overflow and optionally generates interrupts. Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts. Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts. Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts. Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors on block or bit basis in internal registers. Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Allows software to force the AIS insertion on a per tributary basis. Inserts valid H4 byte and all-zeros fixed stuff bytes. Remaining path overhead bytes (J1, B3, C2,G1, F2, Z3, Z4, Z5) are set to all-zeros. Inserts valid pointers and all-zeros transport overhead bytes on the outgoing Telecom Add bus, with valid control signals. Support in-band error reporting by updating the FEBE, RDI and auxiliary RDI bits in the V5 byte with the status of the incoming stream and remote alarm pins. Calculates and inserts the tributary path BIP-2 error detection code for each tributary. Each one of three SONET/SDH VT/TU Mapper Sections:
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Inserts up to 28 bit asynchronous mapped VT1.5 virtual tributaries into an STS-1 SPE from T1 streams.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Inserts up to 28 bit asynchronous mapped TU-11 tributary units into a STM1/VC4 TUG3 or STM-1/VC3 from T1 streams. Inserts up to 28 byte synchronous mapped VT1.5 virtual tributaries into an STS-1 SPE or TU-11 tributary units into an STM-1/VC3 or TUG3 from a STM-1/VC4. Inserts up to 21 bit asynchronous mapped VT2 virtual tributaries into an STS-1 SPE from E1 streams. Inserts up to 21 bit asynchronous mapped TU-12 tributary units into an STM1/VC4 TUG3 or STM-1/VC3 from E1 or T1 streams. Processes the tributary trace message (J2) of the tributaries carried in each STS1/TUG-3 synchronous payload envelope. Bit asynchronous mapping assigns stuff control bits for all streams independently using an all digital control loop. Stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer. Sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control Extracts up to 28 bit asynchronous mapped VT1.5 virtual tributaries from an STS1 SPE into T1 streams via an optional elastic store. Extracts up to 28 bit asynchronous mapped TU-11 tributary units from an STM1/VC4 TUG3 or STM-1/VC3 into T1 streams via an optional elastic store. Extracts up to 21 bit asynchronous mapped VT2 virtual tributaries from an STS-1 SPE into E1 streams via an optional elastic store. Extracts up to 21 bit asynchronous mapped TU-12 tributary units from an STM1/VC4 TUG3 or STM-1/VC3 into E1 or T1 streams via an optional elastic store. Demapper ignores all transport overhead bytes, path overhead bytes and stuff (R) bits Performs majority vote C-bit decoding to detect stuff requests. Each one of three SONET/SDH DS3 Mapper Sections:
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Maps a DS3 stream into an STS-1 SPE (AU3). Sets all fixed stuff (R) bits to zeros or ones per microprocessor control
PROPRIETARY AND CONFIDENTIAL
9
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Extracts a DS3 stream from an STS-1 SPE (AU3). Demapper ignores all transport overhead bytes, path overhead bytes and stuff (R) bits Performs majority vote C-bit decoding to detect stuff requests Complies with DS3 to STS-1 asynchronous mapping standards Each one of three DS3 Receiver Sections:
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Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2). Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable. Provides indication of M-frame boundaries from which M-subframe boundaries and overhead bit positions in the DS3 stream can be determined by external processing. Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate. Extracts valid X-bits and indicates far end receive failure (FERF). Accumulates up to 65,535 line code violation (LCV) events per second, 65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second. Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel. Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled or interrupt-driven operation. Selectable none, one or two address match detection on first byte of received packet. Programmable pseudo-random test-sequence detection-(up to 232 -1 bit length patterns conforming to ITU-T O.151 standards) and analysis features.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Each one of three DS3 Transmit Sections: * * * * * * Provides the overhead bit insertion for a DS3 stream. Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface Provides B3ZS encoding. Generates an B3ZS encoded 100... repeating pattern to aid in pulse mask testing. Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by internal register bits. Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition. Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the Cbit parity application, C-bit parity error events, and far end block error (FEBE) events. Supports insertion of bit-oriented codes in the C-bit parity far end alarm and control channel. Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation. Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any repeating pattern up to 32 bits. The test pattern can be framed or unframed. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7. M23 Multiplexer Section: * * Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream. Performs required bit stuffing/destuffing including generation and interpretation of C-bits.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Includes required FIFO buffers for rate adaptation in the multiplex path. Allows insertion and detection of per DS2 payload loopback requests encoded in the C-bits to be activated under microprocessor control. Internally generates a DS2 clock for use in integrated M13 or C-bit parity multiplex applications. Alternatively accepts external DS2 clock reference. Allows per DS2 alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control. Allows DS2 alarm indication signal (AIS) to be activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal. Supports C-bit parity DS3 format. DS2 Framer Section:
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Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2). Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3 bit error rate. Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF). Accumulates up to 255 DS2 M-bit or F-bit error events per second. DS2 Transmitter Section:
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Generates the required X, F, and M bits into the transmitted DS2 bit stream. Allows inversion of inserted F or M bits for diagnostic purposes. Provides for transmission of far end receive failure (FERF) and alarm indication signal (AIS) under microprocessor control. Provides optional automatic insertion of far end receive failure (FERF) on detection of out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
M12 Multiplexer Section: * * * * * * * Multiplexes four DS1 or three 2048 kbit/s (according to ITU-T Rec. G.747) bit streams into a single M12 format DS2 bit stream. Performs required bit stuffing including generation and interpretation of C-bits. Includes required FIFO buffers for rate adaptation in the multiplex path. Performs required inversion of second and fourth multiplexed DS1 streams as required by ANSI T1.107 Section 7.2. Allows insertion and detection of per DS1 payload loopback requests encoded in the C-bits to be activated under microprocessor control. Allows per tributary alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control. Allows automatic tributary AIS to be activated upon DS2 out of frame. Each one of three E3 Framer Sections: * * Frames to G.751 and G.832 E3 unchannelized data streams. For G.832, terminates the Trail Trace and either the Network Requirement or the General Purpose data link. Each one of three E3 Transmit Sections: * * Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and diagnostic features. for G.832, the Trail Trace is inserted, and an integral HDLC transmitter is provided to insert either the Network Requirement or the General Purpose data link. Synchronous System Interfaces: * Provides twenty one 8 Mbit/s H-MVIP data interfaces for synchronous access to all the DS0s of all 84 T1 links or all timeslots of all 63 E1s. T1 DS0s are bundled from four T1 links in sequential order, 1-4, 5-8, 9-12, ..., 81-84. E1 timeslots are bundled from 4 E1 links in sequential order, 1-4, 5-8, 9-12, ..., 57-60 and 61-63.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Provides twenty one 8 Mbit/s H-MVIP interfaces for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are repeated over the entire T1 or E1 multi-frame. Provides three 8 Mbit/s H-MVIP interfaces for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface. Optionally, timeslot 0 may be presented instead of timeslot 15. All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals, CMV8MCLK, CMVFP, CMVFPC. H-MVIP access for Channel Associated Signaling is available with the Scaleable Bandwidth Interconnect bus as an optional replacement for CAS access over the SBI bus as well as with the H-MVIP data interface. Common Channel Signaling H-MVIP access is available with the SBI bus, serial PCM and H-MVIP data interfaces. Alarm status, T1 F-bit and inband signaling control is available using otherwise unused bit positions. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s. Scaleable Bandwidth Interconnect (SBI) Bus:
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Provides a high density byte serial interconnect for all framed and unframed TEMUX-84 links. Utilizes an Add/Drop configuration to asynchronously mutliplex up to 84 T1s, 63 E1s or 3 DS3s, with multiple payload or link layer processors. Operates at either 19.44 MHz or 77.76 MHz. External devices can access unframed DS3, framed unchannelized DS3, unframed E3, framed unchannelized E3, unframed (clear channel) T1s, framed T1s, unframed (clear channel) E1s, framed E1s, arbitrary rate clear channel data stream (eg. fractional DS3), transparent virtual tributaries or transparent tributary units over this interface. Framed and unframed T1 access can be selected on a per T1 basis. Framed and unframed E1 access can be selected on a per E1 basis.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Up to three arbitrary rate data streams inserted into and extracted from the SBI via bit serial ports. Synchronous access for T1 DS0 channels or E1 timeslots is supported in a locked format mode. Selectable on a per tributary basis. Transparent VT/TU access can be selected only when tributaries are mapped into SONET/SDH. Transparent VT1.5s and TU-11s can be selected on a per tributary basis in combination with framed and unframed T1s. Transparent VT2s and TU-12s can be selected on a per tributary basis in combination with framed and unframed E1s. Channel associated signaling bits for channelized T1 and E1 are explicitly identified across the bus. Transmit timing is mastered either by the TEMUX-84 or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1, E1, E3 or a DS3.
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PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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APPLICATIONS High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems. High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems. Frame Relay switches and access devices (FRADS) SONET/SDH Add Drop Multiplexers SONET/SDH Terminal Multiplexers M23 Based M13 Multiplexer C-Bit Parity Based M13 Multiplexer Channelized and Unchannelized DS3 Frame Relay Interfaces Optical Access Equipment Digital Access Cross-Connect Systems
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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REFERENCES American National Standard for Telecommunications - Digital Hierarchy Synchronous DS3 Format Specifications, ANSI T1.103-1993 American National Standard for Telecommunications - ANSI T1.105 - "Synchronous Optical Network (SONET) - Basic Description Including Multiplex Structure, Rates, and Formats," October 27, 1995. American National Standard for Telecommunications - ANSI T1.105.02 - "Synchronous Optical Network (SONET) - Payload Mappings," October 27, 1995. American National Standard for Telecommunications - Digital Hierarchy - Formats Specification, ANSI T1.107-1995 American National Standard for Telecommunications - Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1997 American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification, ANSI T1.403-1995 American National Standard for Telecommunications - Customer Installation-toNetwork - DS3 Metallic Interface Specification, ANSI T1.404-1994 American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer 1 Specification, ANSI T1.408-1990 Bell Communications Research, TR-TSY-000009 - Asynchronous Digital Multiplexes Requirements and Objectives, Issue 1, May 1986 Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue 1, October, 1987 Bell Communications Research - Alarm Indication Signal Requirements and Objectives, TR-TSY-000191 Issue 1, May 1986 Bell Communications Research - Wideband and Broadband Digital CrossConnect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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Bell Communications Research - Digital Interface Between The SLCO96 Digital Loop Carrier System And A Local Digital Switch, TR-TSY-000008, Issue 2, August 1987 Bellcore GR-253-CORE - "SONET Transport Systems: Common Criteria," Issue 2, Revision 1, December 1997. Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, TR-NWT-000303, Issue 2, December, 1992 Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993 Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, TR-TSY-000820, Section 5.1, Issue 1, June 1990 AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, TR 54016, September, 1989. AT&T - Accunet T1.5 - Service Description and Interface Specification, TR 62411, December, 1990 ITU Study Group XVIII - Report R 105, Geneva, 9-19 June 1992 ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates, May 1994 ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February, 1994. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994. ETSI ETS 300 417-1-1 - "Transmission and Multiplexing (TM); Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes and performance," January, 1996.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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ETSI, Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) Equipment, Jan 1996 ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991. ITU-T - Recommendation G.732 - Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993. ITU-T Recommendation G.707 - Network Node Interface for the Synchronous Digital Hierarchy, 1996 ITU-T Recommendation G.747 - Second Order Digital Multiplex Equipment Operating at 6312 kbit/s and Multiplexing Three Tributaries at 2048 kbit/s, 1988 ITU-T Recommendation G.775, - Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria, 11/94 ITU-T Recommendation G.783 - Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, April, 1997. ITU-T Recommendation G.823, - The Control of Jitter and Wander within Digital Networks which are Based on the 2048 kbit/s Hierarchy, 03/94 IITU-T Recommendation G.964, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March -995. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993. ITU-T Recommendation O.151 - Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N x 64 kbit/s, October 1992
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
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ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993 International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control procedures - Frame Structure TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 Specification, 1995. Nippon Telegraph and Telephone Corporation - Technical Reference for HighSpeed Digital Leased Circuit Services, Third Edition, 1990. GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994 GO-MVIP, H-MVIP Standard, Release1.1a, 1997
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
4
APPLICATION EXAMPLES Figure 1 Any-Service-Any-Port Application
SBI FREEDM 84A672 APPI
Packet/Cell Interworking Function Utopia
Utopia
Telecom Bus
Spectra 155
TEMUX 84
AAL1gator32
IMA
Figure 1illustrates how frame relay (FREEDM84A672), circuit emulation (AAL1gator32) and ATM inverse multiplexing (IMA84) may all be supported on the same port with a common SBI bus as the enabling technology.
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APPI
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 2 High Density Frame Relay Application
Telecom Bus TEMUX 84 TEMUX 84 TEMUX 84 SBI FREEDM 84A672 FREEDM 84A672 FREEDM 84A672
APPI
APPI
UTOPIA
Spectra 622
Packet/Cell Interworking Function
TEMUX 84
FREEDM 84A672
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UTOPIA
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 3 Fractional DS3 Application
FPGA
SBI Bus
RMFPO
RDATO
RSCLK
IFBWCLK
IFBWEN EFBWEN
DS3 LIU
TMFPO
TEMUX-84
EFBWDREQ EFBWDAT EFBWCLK
TMFPI
TDATI
TICLK
FPGA
44.736 MHz
To support evolving fractional DS3 applications, flow-controlled ports provide access to SBI bus bandwidth. Several non-standard schemes have been devised to use a portion of the DS3 payload. Given that these protocols are subject to change, they are best supported by external programmable logic. Figure 3 illustrates one implementation. Other implementations and applications are possible. In the ingress direction, the framed DS3 is presented to an FPGA, whose responsibility it is to identify the utilitized bits of the payload. Valid bits are indicated to the Ingress Flexible Bandwidth Port via an enable signal, IFBWEN.
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IFBWDAT
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
The bits are collected into bytes by the TEMUX-84 and inserted into the payload of the SBI Drop bus. In the egress direction, an FPGA formats the payload of a DS3, while the TEMUX-84 inserts the DS3 frame overhead. The FPGA contains a data buffer. Based on the DS3 frame alignment dictated by the TMFPO signal, the FPGA inserts bits from the data buffer into the DS3 payload according to the protocol supported. To ensure the data buffer is replenished, the FPGA asserts the EFBWDREQ signal to initiate the transfer of a bit. The Egress Flexible Bandwidth Port responds by asserting EFWBEN coincident with EFWBDAT presenting valid data. The SBI Add bus participates by modulating its SAJUST_REQ output to match the SBI data rate to that required to keep internal FIFOs centered.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
5 5.1
BLOCK DIAGRAM Top Level Block Diagram Figure 4 shows the complete TEMUX-84. T1 links can be multiplexed into the DS3s or can be mapped into the telecom bus as SONET VT1.5 virtual tributaries or as SDH TU-11 or TU-12 tributary units. E1 links can be mapped into the telecom bus as SONET VT2 virtual tributaries or as SDH TU-12 tributary units. System side access to the T1s and E1s is available as Synchronous H-MVIP interfaces or the SBI bus. DS3 line side access is via the clock and data interface for line interface units (LIUs) or DS3 mapped into the SONET/SDH telecom bus. Unchannelized DS3 system side access is available through the SBI bus. Figure 4 TEMUX-84 Block Diagram
LIU s
M13 M13 D3MA
DS3/E3 Tx System I/F
M13 M13 DS3/E3 TRA N
M13 M13 M13
M13 M13 PISO
Transmux datapath
Egres s Flexible B/W Port Egres s H-MVIP
Telec om B us
M13 M13 VTPP TTOP TRAP
IN SBI (by te) TTMP (bit) T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRMR84 T1/E1 ELST84 T1/E1 ELST84
H-MVIP
EXSBI
SBI 155
IN SBI T1/E1 SIGX84 Ingress H-MVIP
M13 M13 VTPP
M13 M13 RTOP/ RTTB
RTDM (bit) EXSBI (by te)
Telec om B us
M13 M13 D3MD M13 M13 DS3/E3 FRMR M13 M13 M13
M13 M13 SIPO
Ingress Flexible B/W Port
H-MVIP
LIU s
DS3/E3 Rx System I/F
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
5.2
M13 Multiplexer Mode Block Diagram Figure 5 shows the TEMUX-84, configured as a M13 multiplexer, connected to a synchronous H-MVIP system side bus. In this example the TEMUX-84 provides synchronous access to the fully channelized T1s (access to all DS0s) multiplexed into the DS3. There is also synchronous H-MVIP access to all channel associated signaling channels (CAS). Additional H-MVIP interfaces can be used to provide synchronous access to the common channel signaling channels (CCS), although this same information is available within the data H-MVIP signals. Figure 5 M13 Multiplexer Block Diagram
LIUs
M13 M 13 DS3 TRAN M13 M13 M13 PISO T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRMR84 T1/E1 ELST84 T1/E1 ELST84 Egress H-M VIP
H-M VIP
LIUs
M13 M 13 DS3 FRMR
M13 M13 M 13
SIPO
T1/E1 SIGX84
Ingress H-M VIP
H-M VIP
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
5.3
VT/TU Mapper Only Mode Block Diagram Figure 6 shows the TEMUX-84 configured as a VT or TU mapper. In this mode the TEMUX-84 bypasses the T1 and E1 framers and provides access for up to 84 independent unframed 1.544 Mbit/s streams or 63 independent unframed 2.048 Mbit/s streams. The 1.544 Mbit/s and 2.048 Mbit/s streams can be accessed on the system side via the SBI bus. The T1 or E1 framers can be used to monitor the passing traffic in either the ingress or egress direction. The M13 Multiplexer mode operates in much the same way as the VT and TU mapper shown in Figure 6. Figure 6 VT/TU Mapper Block Diagram
M 13 M 13 VTPP INSBI TTM P (bit) M 13 M 13 VTPP M 13 M 13 RTOP/ RTTB RTDM (bit) EXSBI T1/E1 JAT84 T1/E1 JAT84 EXSBI T1/E1 FRM R84 INSBI
TTOP
TRAP
Telecom Bus
SBI 155
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
5.4
DS3/E3 Framer Only Block Diagram Figure 7 shows the TEMUX-84 configured as a DS3 or E3 framer. In this mode the TEMUX-84 provides access up to three full DS3/E3 unchannelized payloads. The payload access (right side of diagram) has two clock and data interfacing modes, one utilizing a gapped clock to mask out the DS3/E3 overhead bits and the second utilizing an ungapped clock with overhead indications on a separate overhead signal. The SBI bus can also be used to provide access to the unchannelized DS3/E3. Figure 7 DS3/E3 Framer Only Mode Block Diagram
TDP R Tx HD LC TIC LK TCLK TPO S/TD AT TNEG/TM FP TRAN DS3/E3 Transm it Fram er FRM R DS3/E3 R eceive Fram er PMO N Perf. M onitor
B3ZS/ HDB 3 E ncode
TD A TI TFP O/TMFPO /TG APC LK TFP I/T M FP I RG APCLK/RSCLK RD ATO RFPO /R MFPO RO VRHD
RCLK/VCLK RPOS /RD AT RNEG /R LC V
B3ZS/ HD B3 Decode
RDLC Rx HDLC
3X
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
6
DESCRIPTION The PM8316 High Density T1/E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers (TEMUX-84) is a feature-rich device for use in any applications requiring high density link termination over T1 and E1 (G.747) channelized DS3 or T1 and E1 channelized SONET/SDH facilities. The TEMUX-84 supports asynchronous multiplexing and demultiplexing of 84 DS1s or 63 E1s into three DS3 signals as specified by ANSI T1.107, Bell Communications Research TR-TSY-000009 and ITU-T Rec. G.747. It supports bit asynchronous or byte synchronous mapping and demapping of 84 T1s or 63 E1s into SONET/SDH as specified by ANSI T1.105, Bell Communications Research GR-253-CORE and ITU-T Recommendation G.707. The TEMUX-84 also supports mapping of 63 T1s into SDH via TU-12s. Up to 84 Transparent VT1.5s and TU-11s or 63 Transparent VT2s and TU-12s can be transferred between the SONET/SDH interface and the SBI bus interface. This device can also be configured as a DS3 or E3 framer, providing external access to the full DS3 or E3 payload, or a VT/TU mapper, providing access to unframed 1.544 Mbit/s and 2.048 Mbit/s links. The TEMUX-84 can be used as a SONET/SDH VT/TU mapper or M13 multiplexer with performance monitoring in either the ingress or egress direction for up to 84 T1s or 63 E1s. In this configuration the T1 and E1 transmit framers are disabled and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers for performance monitoring purposes, which include error event accumulation, alarm monitoring and HDLC termination. Each of the T1 and E1 framers and transmitters is independently software configurable, allowing timing master and feature selection without changes to external wiring. T1 and E1 tributaries may be mixed at a VC-3/TUG-3/DS3 granularity. In the ingress direction, each of the 84 T1 links is either demultiplexed from a channelized DS3 or extracted from SONET VT1.5, TU-11 or TU-12 mapped bus. Each T1 framer can be configured to frame to the common DS1 signal formats (SF, SLCO96, ESF) or to be bypassed (unframed mode). Each T1 framer detects the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. T1 performance monitoring with accumulation of CRC-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. The TEMUX84 also detects the presence of ESF bit oriented codes, and detects and
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
terminates HDLC messages on the ESF data link. The HDLC messages are terminated in a 128 byte FIFO. An elastic store that optionally supports slip buffering and adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing and interrupt on signaling state change on a per-DS0 basis. The TEMUX-84 also supports inband loopback code generation and detection, idle code substitution, digital milliwatt code insertion, data link extraction, trunk conditioning, data sign and magnitude inversion, and pattern generation and detection on a per-DS0 basis. In the egress direction, framing is generated for 84 T1s into either a DS3 multiplex or a SONET/SDH mapped add bus. Each T1 transmitter frames to SF or ESF DS1 formats, or framing can be optionally disabled. The TEMUX-84 supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion and zero-code suppression on a per-DS0 basis. PRBS generation and detection is supported on a framed and unframed T1 basis. In the ingress direction, each of the 63 E1 links is either demultiplexed from a DS3 according to ITU-T Rec. G.747 or extracted from SONET/SDH VT2 or TU-12 mapped bus. Each E1 framer detects and indicates the presence of remote alarm and AIS patterns and also integrates Red and AIS alarms. The E1 framers support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal. E1 performance monitoring with accumulation of CRC-4 errors, far end block errors and framing bit errors is provided. The TEMUX-84 provides a receive HDLC controller for the detection and termination of messages on the national use bits. Detection of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. V5.2 link ID signal detection is also supported. An interrupt may be generated on any change of state of the Sa codewords. An elastic store for slip buffering and rate adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided. In the egress direction, framing is generated for 63 E1s into either a DS3 multiplex according to ITU-T Rec. G.747 or a SONET/SDH mapped add bus. Each E1 transmitter generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Transmission of the
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS generation or detection is supported on a framed and unframed E1 basis. The TEMUX-84 can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. Three jitter attenuated recovered T1/E1 clocks can be routed outside the TEMUX-84 for network timing applications. In synchronous backplane systems, 8 Mbit/s H-MVIP interfaces are provided for access to 2016 DS0 channels, channel associated signaling (CAS) for all 2016 DS0 channels and common channel signaling (CCS) for all 84 T1s or 63 E1s (or combination thereof). The CCS signaling H-MVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1 slip buffers. A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s or 63 E1 both synchronously or asynchronously. The SBI allows transmit timing to be mastered by either the TEMUX-84 or link layer device connected to the SBI bus. In addition to framed T1s and E1s the TEMUX-84 can transport unframed T1 or E1 links and framed or unframed DS3 or E3 links over the SBI bus. When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TEMUX84 accepts and outputs either digital B3ZS-encoded bipolar or unipolar signals compatible with M23 and C-bit parity applications. In the DS3 receive direction, the TEMUX-84 frames to DS3 signals with a maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, Cbit parity errors, far end block errors, AIS, far end receive failure and idle code. The DS3 framer is an off-line framer, indicating both out of frame (OOF) and change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still indicated while the framer is OOF, based on the previous frame alignment. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC channels are detected and are available through the microprocessor port. Error event accumulation is also provided by the TEMUX-84. Framing bit errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, and far end block errors are accumulated. Error accumulation continues even while the off-line framers are indicating OOF. The counters are intended to
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
be polled once per second, and are sized so as not to saturate at a 10-3 bit error rate. Transfer of count values to holding registers is initiated through the microprocessor interface. In the DS3 transmit direction, the TEMUX-84 inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals, Far End Receive Failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M sub-frame) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity application. Transmit timing is from an external reference or from the receive direction clock. The TEMUX-84 also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo Random Binary Sequence (PRBS) can be inserted into a DS3 payload and checked in the receive DS3 payload for bit errors. A fixed 100100... pattern is available for insertion directly into the B3ZS encoder for proper pulse mask shape verification. The TEMUX-84 may be used as an E3 framer for the transport of framed but unchannelized E3 data streams complying to the ITU-T Recommendations G.751 or G.832. The line interface may be configured as either unipolar or HDB3encoded. When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of each DS3 signal. Bit stuffing and rate adaptation is performed. The C-bits are set appropriately, with the option of inserting DS2 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS3. AIS may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a stuffing ratio of 100%. Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far end receive failure is detected and M-bit and F-bit errors are accumulated. The DS2 framer is an off-line framer, indicating both OOF and COFA events. Error
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated while the DS2 framer is indicating OOF, based on the previous alignment. Each of the seven 6312 kbit/s multiplexers per DS3 may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s or three 2048 kbit/s according to ITU-T Rec. G.747 into and out of a DS2 formatted signal. Tributary frequency deviations are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. When configured as a DS3 or E3 framer the unchannelized payload of the DS3 and E3 links are available to an external device. The SONET/SDH line side interface provides STS-1 SPE synchronous payload envelope processing and generation, TUG3 tributary unit group processing and generation within a VC4 virtual container and VC3 virtual container processing and generation. The payload processor aligns and monitors the performance of SONET virtual tributaries (VTs) or SDH tributary units (TUs). Maintenance functions per tributary include detection of loss of pointer, AIS alarm, tributary path signal label mismatch and tributary path signal label unstable alarms. Optionally interrupts can be generated due to the assertion and removal of any of the above alarms. Counts are accumulated for tributary path BIP-2 errors on a block or bit basis and for FEBE indications. The synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary path BIP-2. The generator also inserts FEBE, RDI and enhanced RDI in the V5 byte. Software can force AIS insertion on a per tributary basis. A SONET/SDH mapper maps and demaps up to 84 T1s, 63 E1s or three DS3s into three STS-1 SPEs, TUG3s or VC3s through three elastic stores. The fixed stuff (R) bits are all set to zeros or ones under microprocessor control. The bit asynchronous demapper performs majority vote C-bit decoding to detect stuff requests for T1, E1 and DS3 asynchronous mappings. The VT1.5/VT2/TU11/TU-12 mapper uses an elastic store and a jitter attenuator capability to minimize jitter introduced via bit stuffing. The TEMUX-84 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
7
PIN DIAGRAM The TEMUX-84 is packaged in a 324-pin PBGA package having a body size of 23mm by 23mm and a ball pitch of 1.0 mm. The center 36 balls are not used as signal I/Os and are thermal balls. Pin names and locations are defined in the Pin Description Table in section 8. Mechanical information for this package is in the section 19. Figure 8 Pin Diagram
22 21 20 19 18 17 16 15 14 13 12 11 10 A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VSS VSS VSS VSS VSS VSS
9
8
7
6
5
4
3
2
1
324 PBGA
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Bottom View
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
8
PIN DESCRIPTION Type Pin Function No.
Pin Name
DS3 and E3 Line Side Interface RCLK[3] RCLK[2] RCLK[1] RPOS/RDAT[3] RPOS/RDAT[2] RPOS/RDAT[1] Input P1 T1 Y1 P2 U1 V3 Receive Input Clocks (RCLK[3:1]). RCLK[3:1] provide the receive direction timing for the three DS3s or E3s. RCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clock inputs. Positive Input Pulse (RPOS[3:1]). RPOS[3:1] represent the positive pulses received on the B3ZSencoded DS3s or HDB3-encoded E3s when dual rail input format is selected. Receive Data Input (RDAT[3:1]). RDAT[3:1] represent the NRZ (unipolar) DS3 or E3 input data streams when single rail input format is selected. RPOS[3:1] and RDAT[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of the associated RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register. RNEG/RLCV[3] RNEG/RLCV[2] RNEG/RLCV[1] Input P3 T3 W2 Negative Input Pulse (RNEG[3:1]). RNEG[3:1] represent the negative pulses received on the B3ZSencoded DS3s or HDB3-encoded E3s when dual rail input format is selected. Line code violation (RLCV[3:1]). RLCV[3:1] represent receive line code violations when single rail input format is selected. RNEG[3:1] and RLCV[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register. TCLK[3] TCLK[2] TCLK[1] Output R3 V1 W3 Transmit Clock (TCLK[3:1]). TCLK[3:1] provide timing for circuitry downstream of the DS3 and E3 transmitters of the TEMUX-84. TCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks.
Input
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TPOS/TDAT[3] TPOS/TDAT[2] TPOS/TDAT[1]
Type
Pin Function No.
Output R2 Transmit Positive Pulse (TPOS[3:1]). TPOS[3:1] U2 represent the positive pulses transmitted on the B3ZSAA1 encoded DS3 or HDB3-encoded E3 lines when dualrail output format is selected. Transmit Data Output (TDAT[3:1]). TDAT[3:1] represent the NRZ (unipolar) DS3 output data streams when single rail output format is selected. TPOS[3:1] and TDAT[3:1] are updated on the falling edge of the associated TCLK by default but may be enabled to be updated on the rising edge of the associated TCLK by setting the TRISE bit in the DS3/E3 Master Transmit Line Options register. TPOS[3:1] and TDAT[3:1] are updated on TICLK[3:1] rather than TCLK[3:1] when the TICLK bit in the DS3/E3 Master Transmit Line Options register is set.
TNEG/TMFP[3] TNEG/TMFP[2] TNEG/TMFP[1]
Output U4 Transmit Negative Pulse (TNEG[3:1]). TNEG[3:1] W1 represent the negative pulses transmitted on the AB1 B3ZS-encoded DS3 or HDB3-encoded E3 lines when dual-rail output format is selected. Transmit Multiframe Pulse (TMFP[3:1]). These signals mark the transmit frame alignment when configured for single rail operation. TMFP[3:1] indicate the position of overhead bits in the transmit transmission system stream, TDAT[3:1]. TMFP[3:1] are high during the first bit (X1) of the multiframe or E3 frame. TNEG[3:1] and TMFP[3:1] are updated on the falling edge of the associated TCLK by default but may be enabled to be updated on the rising edge of the associated TCLK by setting the TRISE bit in the DS3/E3 Master Transmit Line Options register. TNEG[3:1] and TMFP[3:1] are updated on TICLK[3:1] rather than TCLK[3:1] when the TICLK bit in the DS3/E3 Master Transmit Line Options register is set.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TICLK[3] TICLK[2] TICLK[1]
Type Input
Pin Function No. T4 V4 Y2 Transmit input clock (TICLK[3:1]). TICLK[3:1] provides the transmit direction timing for the three DS3s or E3s. TICLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks. Framer Recovered Gapped Clock (RGAPCLK[3:1]). RGAPCLK[3:1] are valid when the TEMUX-84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register. RGAPCLK[x] is the recovered clock and timing reference for RDATO[x]. RGAPCLK[3:1] are held either high or low during bit positions which correspond to overhead. Framer Recovered Clock (RSCLK[3:1]). RSCLK[3:1] are valid when the TEMUX-84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. When a DS3 is demapped from SONET/SDH (i.e. LINEOPT_SPEx = 01), RSCLK is a gapped version of CLK52M. RSCLK[3:1] are the recovered clocks and timing references for RDATO[3:1], RFPO/RMFPO[3:1], and ROVRHD[3:1].
DS3 and E3 System Side Interface RGAPCLK/RSCLK Output H4 [3] RGAPCLK/RSCLK L3 [2] RGAPCLK/RSCLK N3 [1]
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name RDATO[3] RDATO[2] RDATO[1]
Type
Pin Function No. Framer Receive Data (RDATO[3:1]). RDATO[3:1] are valid when the TEMUX-84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. RDATO[3:1] are the received data aligned to RFPO/RMFPO[3:1] and ROVRHD[3:1]. RDATO[3:1] are updated on either the falling or rising edge of the associated RGAPCLK or RSCLK, depending on the value of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register. By default, RDATO[3:1] will be updated on the falling edge of the associated RGAPCLK[3:1] or RSCLK[3:1].
Output H2 K4 N2
RFPO/RMFPO[3] RFPO/RMFPO[2] RFPO/RMFPO[1]
Output H1 K2 M2
Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[3:1]). RFPO/RMFPO[3:1] are valid when the TEMUX-84 is configured to be in framer only mode by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. RFPO[3:1] are aligned to RDATO[3:1] and indicate the position of the first bit in each DS3 M-subframe and the first bit in each G.751 E3 or G.832 E3 frame. RMFPO[3:1] are aligned to RDATO[3:1] and indicate the position of the first bit in each DS3 M-frame and the first bit in each G.751 or G.832 E3 frame. This is selected by setting the RXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options Registers. RFPO/RMFPO[3:1] are updated on either the falling or rising edge of the associated RSCLK depending on the setting of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name ROVRHD[3] ROVRHD[2] ROVRHD[1]
Type
Pin Function No. Framer Receive Overhead (ROVRHD[3:1]). ROVRHD[3:1] are valid when the TEMUX-84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. ROVRHD[3:1] will be high whenever the data on RDATO[3:1] corresponds to an overhead bit position. ROVRHD[3:1] is updated on the either the falling or rising edge of the associated RSCLK depending on the setting of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register.
Output H3 K1 N1
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TFPO/TMFPO/ TGAPCLK[3] TFPO/TMFPO/ TGAPCLK[2] TFPO/TMFPO/ TGAPCLK[1]
Type
Pin Function No. Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[3:1]). TFPO/TMFPO[3:1] are valid when the TEMUX-84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and setting the TXGAPEN bit to 0 in the DS3 and E3 Master Unchannelized Interface Options register. In DS3 mode, TFPO[3:1] pulse high for 1 out of every 85 clock cycles, giving a reference M-subframe indication. In E3 mode, TFPO[3:1] pulse high to mark the first bit of the frame. In DS3 mode, TMFPO[3:1] pulse high for 1 out of every 4760 clock cycles, giving a reference M-frame indication. TMFPO[3:1] behaves the same as TFPO[3:1] for E3 applications. This is selected by setting the TXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options Registers. TFPO/TMFPO[3:1] will be updated on the falling edge of TICLK when the associated TDATIFALL register bit is a logic 0 and on the rising edge when TDATIFALL is a logic 1. Framer Gapped Transmit Clock (TGAPCLK[3:1]). TGAPCLK[3:1] are valid when the TEMUX-84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers and setting the TXGAPEN bit to 1 in the DS3 and E3 Master Unchannelized Interface Options register. TGAPCLK[3:1] are derived from the transmit reference clocks TICLK[3:1] or from the receive clock if looptimed. The overhead bit (gapped) positions are generated internal to the device. TGAPCLK[3:1] are held high during the overhead bit positions. This clock is useful for interfacing to devices which source payload data only. TGAPCLK[3:1] are used to sample the associated TDATI[3:1] inputs.
Output F4 J4 M3
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TDATI[3] TDATI[2] TDATI[1]
Type Input
Pin Function No. G2 J3 L2 Framer Transmit Data (TDATI[3:1]). TDATI[3:1] contain the serial data to be transmitted when the TEMUX-84 is configured as DS3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. TDATI[3:1] are sampled on the rising edge of the associated TICLK if the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0. If TXGAPEN is logic 1, then TDATI[3:1] are sampled on the rising edge of TGAPCLK. TDATI[3:1] can be configured to be sampled on the falling edge of the associated TICLK or TGAPCLK by setting the TDATIFALL bit in the DS3 and E3 Master Unchannelized Interface Options register. Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[3:1]). TFPI/TMFPI[3:1] are valid when the TEMUX-84 is configured as DS3 or E3 framers by setting the OPMODE_SPEx[2:0] bits in the SPE Configuration registers. TFPI[3:1] indicate the position of all overhead bits in each DS3 M-subframe or the first bit in each G.751 E3 or G.832 E3 frame. TFPI[3:1] are not required to pulse at every overhead bit. TMFPI[3:1] indicate the position of the first bit in each 4760-bit DS3 M-frame or the first bit in each E3 frame. TMFPI[3:1] are not required to pulse at every multiframe boundary. This is selected by setting the TXMFPI bit in the DS3 and E3 Master Unchannelized Interface Options Registers. TFPI/TMFPI[3:1] are sampled on the rising edge of the associated TICLK. TDATI[3:1] can be configured to be sampled on the falling edge of the associated TICLK by setting the TDATIFALL bit to 1 in the DS3 and E3 Master Unchannelized Interface Options register.
TFPI/TMFPI[3] TFPI/TMFPI[2] TFPI/TMFPI[1]
Input
G1 J1 M1
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name
Type
Pin Function No.
H-MVIP System Side Interfaces CMV8MCLK Input T22 Common 8M H-MVIP Clock (CMV8MCLK). The common 8.192 Mbit/s H-MVIP data provides the data clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode. CMV8MCLK is used to sample data on MVID[1:21], MVED[1:21], CASID[1:21], CASED[1:21], CCSID[1:3], CCSED[1:3] and TS0ID. CMV8MCLK is nominally a 50% duty cycle clock with a frequency of 16.384 MHz. The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration register. If the TEMUX-84 is not configured for H-MVIP operation, this clock may be tied high or low. CMVFPC Input R20 Common H-MVIP Frame Pulse Clock (CMVFPC). The common 8.192 Mbit/s H-MVIP frame pulse clock provides the frame pulse clock for receive and transmit links configured for operation in 8.192 Mbit/s H-MVIP mode. CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC must be aligned with the falling edge of CMV8MCLK with no more than 10ns skew. The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration registers. If the TEMUX-84 is not configured for H-MVIP operation, this clock may be tied high or low.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name CMVFPB
Type Input
Pin Function No. R22 Common H-MVIP Frame Pulse (CMVFPB). The active low common frame pulse for 8.192 Mbit/s HMVIP signals references the beginning of each frame for links operating in 8.192 Mbit/s H-MVIP mode. If the CMMFP bit of the Master H-MVIP Interface Configuration register is a logic 1, the CMVFPB is becomes a multiframe pulse. Mulitframe alignment is only relevant when the T1 F-bit or the E1 TS0 is being carried transparently in the egress direction and alignment to CAS signaling is required. To support any combination of SF, SLCO96, ESF and E1, the CMVFPB must pulse low at a multiple of 48 frames at the beginning of the frame. The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration register. If the TEMUX-84 is not configured for H-MVIP operation, this frame pulse may be tied high or low. The CMVFPB frame pulse occurs at multiples of 125us and is sampled on the falling edge of CMVFPC.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name MVID[1] MVID[2] MVID[3] MVID[4] MVID[5] MVID[6] MVID[7] MVID[8] MVID[9] MVID[10] MVID[11] MVID[12] MVID[13] MVID[14] MVID[15] MVID[16] MVID[17] MVID[18] MVID[19] MVID[20] MVID[21]
Type
Pin Function No. H-MVIP Ingress Data (MVID[1:21]). MVID[x] carries the recovered T1 or E1 channels which have passed through the elastic store. Each MVID[x] signal carries the channels of four complete T1s or E1s. MVID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is updated on every second rising or falling edge of the common H-MVIP 16.384Mb /s clock, CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master and H-MVIP Interface Configuration register. T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of MVID[1:7], MVID[8:14] and MVID[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, MVID[7], MVID[14] and MVID[21] are unused.
Output B3 A3 A2 C5 A4 B5 C6 A5 B6 C7 D6 A6 A7 C8 B8 A8 D7 C9 B9 A9 D9
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name CASID[1] CASID[2] CASID[3] CASID[4] CASID[5] CASID[6] CASID[7] CASID[8] CASID[9] CASID[10] CASID[11] CASID[12] CASID[13] CASID[14] CASID[15] CASID[16] CASID[17] CASID[18] CASID[19] CASID[20] CASID[21] CCSID[1] CCSID[2] CCSID[3]
Type
Pin Function No. Channel Associated Signaling Ingress Data (CASID[1:21]). Each CASID[x] signal carries CAS for four complete T1s or E1s. CASID[x] carries the corresponding CAS values of the channel carried in MVID[x]. It also carries the framer and alarm statuses. CASID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASID[x] is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register. T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of CASID[1:7], CASID[8:14] and CASID[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, CASID[7], CASID[14] and CASID[21] are unused.
Output B18 A19 A20 B19 B20 A21 B21 D20 B22 C21 D21 E20 E21 C20 E22 F21 E19 G20 F22 G21 G22
Output C16 Common Channel Signaling Ingress Data D18 (CCSID[1:3]). In T1 mode, CCSID[1] carries the 84 B17 common channel signaling channels extracted from each of the 84 T1s. In E1 mode, CCSID[1:3] carries up to 3 timeslots (15,16, 31) from each of the 63 E1s. CCSID is formatted according to the H-MVIP standard. CCSID[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSID is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TS0ID
Type
Pin Function No.
Output D17 E1 Timeslot 0 Ingress Data (TS0ID). In E1 mode, TS0ID carries the first timeslot of each frame. TS0ID is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. TS0ID is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register.
MVED[1] MVED[2] MVED[3] MVED[4] MVED[5] MVED[6] MVED[7] MVED[8] MVED[9] MVED[10] MVED[11] MVED[12] MVED[13] MVED[14] MVED[15] MVED[16] MVED[17] MVED[18] MVED[19] MVED[20] MVED[21]
Input
B10 A10 D10 B11 A11 D12 B12 C12 D13 B13 C13 D14 A14 B14 C14 A15 B15 A16 C15 B16 A17
H-MVIP Egress Data (MVED[1:21]). The egress data streams to be transmitted are input on these pins. Each MVED[x] signal carries the channels of four complete T1s or E1s formatted according to the HMVIP standard. MVED[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of MVED[1:7], MVED[8:14] and MVED[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, MVED[7], MVED[14] and MVED[21] are unused.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name CASED[1] CASED[2] CASED[3] CASED[4] CASED[5] CASED[6] CASED[7] CASED[8] CASED[9] CASED[10] CASED[11] CASED[12] CASED[13] CASED[14] CASED[15] CASED[16] CASED[17] CASED[18] CASED[19] CASED[20] CASED[21] CCSED[1], CCSED[2], CCSED[3]
Type Input
Pin Function No. H19 J20 J21 J22 J19 K20 K22 K19 L20 L22 M22 M21 M20 N19 N22 N20 P19 P22 P21 P20 R19 Channel Associated Signaling Egress Data (CASED[1:21]). Each CASED[x] signal carries CAS for four complete T1s or E1s formatted according to the H-MVIP standard. CASED[x] carries the corresponding CAS values of the channel data carried in MVED[x]. CASED[x] may also present inband information for the control of signaling insertion. CASED[x] is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASED[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master H-MVIP Interface Configuration register. T1 and E1 links may be mixed on a TUG-3/DS3 granularity. Each of CASED[1:7], MVED[8:14] and CASED[15:21] carries 28 T1s or 21 E1s independent of the other two groups of seven. For E1 mode, CASED[7], CASED[14] and CASED[21] are unused.
Input
H20 Common Channel Signaling Egress Data H21 (CCSED[1:3]). In T1 mode CCSED[1] carries the H22 common channel signaling channels to be transmitted in each of the T1s. In E1 mode CCSED carries up to 3 timeslots (15,16, 31) to be transmitted in each of the E1s. CCSED is formatted according to the H-MVIP standard. CCSED is aligned to the common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSED is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master H-MVIP Interface Configuration register.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name
Type
Pin Function No.
Flexible Bandwidth Ports Port #1 is associated with SBI SPE #1. Port #2 is associated with SBI SPE #2. Port #3 is associated with SBI SPE #3. IFBWCLK[3] IFBWCLK[2] IFBWCLK[1] Input N22 The Ingress Flexible Bandwidth Clocks K19 (IFBWCLK[3:1]). The IFBWCLK[3:1] clocks provide H19 the timing for an arbitrary bandwidth payload to be inserted into the System Drop Bus (SDDATA[7:0]). Each clock is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. IFBWCLK[3:1] may have a maximum frequency of 51.84 MHz and may be gapped if required. Each IFBWCLK samples the associated IFBWDAT[3:1] and IFBWEN[3:1] inputs on the rising edge. IFBWDAT[3] IFBWDAT[2] IFBWDAT[1] Input N20 The Ingress Flexible Bandwidth Data L20 (IFBWDAT[3:1]). These inputs present bit serial data J20 for insertion into the System Drop Bus (SDDATA[7:0]). Only bits for which the associated IFBWEN input is sampled high are accepted. Each data input is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. IFBWDAT[3:1] are sampled on the rising edge of the associated IFBWCLK input. IFBWEN[3] IFBWEN[2] IFBWEN[1] Input P19 The Ingress Flexible Bandwidth Enables L22 (IFBWEN[3:1]). A logic high on any of these inputs J21 indicates a valid bit on the associated IFBWDAT input. The IFBWEN[3:1] inputs are constrained such that the maximum data rate of each of IFBWDAT[3:1] is less than 48.96 Mbit/s. IFBWEN[3:1] are sampled on the rising edge of the associated IFBWCLK input.
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name EFBWCLK[3] EFBWCLK[2] EFBWCLK[1]
Type Input
Pin Function No. P22 The Egress Flexible Bandwidth Clocks M22 (EFBWCLK[3:1]). The EFBWCLK[3:1] clocks provide J22 the timing for an arbitrary bandwidth payload extracted from the System Add Bus (SADATA[7:0]). Each clock is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. EFBWCLK[3:1] may have a maximum frequency of 51.84 MHz and may be gapped if required. Each EFBWCLK samples the associated EBWDREQ on the rising edge and updates the associated EFBWDAT] and EFBWEN on the falling edge.
EFBWDREQ[3] EFBWDREQ[2] EFBWDREQ[1]
Input
P21 The Egress Flexible Bandwidth Data Requests M21 (EFBWREQ[3:1]). The data request input must be J19 asserted high for a EFBWCLK cycle for each bit of data required. In response to sampling EFWBDREQ[3:1] high, the associated EFBWDAT output will either present an available bit a cycle later with an accompanying assertion of the associated EFBWEN or ignore the request if no data is ready. In many applications (eg. frame relay and ATM), every request will be acknowledged with data. In applications where the source data is fixed, it is permissible to hold EFBWDREQ[3:1] high, in which case EFBWEN identifies valid bytes. EFBWDREQ[3:1] are sampled on the rising edge of the associated EFBWCLK input.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name EFBWDAT[3] EFBWDAT[2] EFBWDAT[1]
Type
Pin Function No.
Output F21 The Egress Flexible Bandwidth Data B22 (EFBWDAT[3:1]). These outputs present bit serial A19 data extracted from the System Add Bus (SADATA[7:0]). Only bits for which the associated EFBWEN output is simultaneously high are valid. Each data input is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. EFBWDAT[3:1] are updated on the falling edge of the associated EFBWCLK input.
EFBWEN[3] EFBWEN[2] EFBWEN[1]
Output E22 The Egress Flexible Bandwidth Enables D20 (EFBWEN[3:1]). A logic high on any of these outputs B18 indicates a valid bit on the associated EFBWDAT output. The EFBWEN[3:1] will only be asserted, with a one cycle latency, in response to a sampled logic high on the associated EFBWDREQ, and then only if data is available for presenting on the associated EFBWDAT. EFBWEN[3:1] are updated on the falling edge of the associated EFBWCLK input.
Recovered T1 and E1 Clocks RECVCLK1 Output F2 Recovered Clock 1 (RECVCLK1). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers. Recovered Clock 2 (RECVCLK2). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers. Recovered Clock 3 (RECVCLK3). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers or 63 E1 framers.
RECVCLK2
Output E4
RECVCLK3
Output G3
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name XCLK_T1
Type Input
Pin Function No. E2 T1 Crystal Clock Input (XCLK_T1). This input clocks the digital phase locked loop that performs jitter attenuation on the T1 recovered clocks which drive the RECVCLK1/2/3 outputs. XCLK_T1 is nominally a 37.056 MHz 32ppm, 50% duty cycle clock. This input may be tied to ground in applications that do not use the RECVCLK1/2/3 outputs as s1.544 MHz clocks.
XCLK_E1
Input
F3
E1 Crystal Clock Input (XCLK_E1). This input clocks the digital phase locked loop that performs jitter attenuation on the E1 recovered clocks which drive the RECVCLK1/2/3 outputs. XCLK_E1 is nominally a 49.152 MHz 32ppm, 50% duty cycle clock when configured for E1 modes. This input may be tied to ground in applications that do not use the RECVCLK1/2/3 outputs as 2.048 MHz clocks.
Telecom Line Side Interface LREFCLK Input Y4 Line Reference Clock (LREFCLK). This signal provides reference timing for the SONET telecom bus interface. On the incoming byte interface of the telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL, LDTPL, LDV5, LDAIS and LAC1 are sampled of the rising edge or LREFCLK. In the outgoing byte interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 and LAOE/LATPL are updated on the rising edge of LREFCLK. This clock may be held low if the Telecom Bus interface is unused. This clock is nominally a 19.44 MHz +/-50ppm or 77.76 MHz +/-50ppm clock with a 50% duty cycle. This clock must be phase locked to SREFCLK and can be external connected to SREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name L77
Type Input
Pin Function No. AA4 The Line 77.76 MHz select input determines the expected frequency of LREFCLK. If L77 is low, LREFCLK is expected to be 19.44 MHz. If L77 is high, LREFCLK is expected to be 77.76 MHz and data is driven and sampled every fourth cycle. L77 is expected to be held static. W10 Line Add C1 Frame Pulse (LAC1). The Add bus timing signal identifies the frame and multiframe boundaries on the Add Data bus LADATA[7:0]. LAC1 is set high to mark the first C1 byte of the first transport envelope frame of the 4 frame multiframe on the LADATA[7:0] bus. LAC1 need not be presented on every occurrence of the multiframe . LAC1 is sampled on the rising edge of LREFCLK.
LAC1
Input
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LAC1J1V1
Type
Pin Function No.
Output AA11 Line Add Bus Composite Timing Signal (LAC1J1V1). The Add bus composite timing signal identifies the frame, payload and tributary multiframe boundaries on the Line Add Data bus LADATA[7:0]. LAC1J1V1 pulses high with the Line Add Payload Active signal LAPL set low to mark the first STS-1 (STM-0/AU3) identification byte or equivalently the STM identification byte C1. Optionally the LAC1J1V1 signal pulses high with LAPL set high to mark the path trace byte J1. Optionally the LAC1J1V1 signal pulses high on the V1 byte to indicate tributary multiframe boundaries. In a system with multiple TEMUX-84s sharing the same Line Add bus only one device should have LAC1J1V1 connected. All devices must be configured via the TXPTR[9:0] bits in the SONET/SDH Transmit Pointer Configuration and TTMP Telecom Interface Configuration registers for the same J1 location. When L77 high, LAC1J1V1 is only valid (i.e. identifies the first C1, J1 and V1 of the concatenated STM-4 data stream) if the LSTM[1:0] bits in the Master Bus Configuration register (0x0006) are set to "00". LAC1J1V1 is updated on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LAOE/LATPL
Type
Pin Function No.
Output AB11 The LATPLSEL bit of the SONET/SDH Master Egress VTPP Configuration register determines the function of this output. When LATPLSEL is logic 1, the signal is LATPL. When LATPLSEL is logic 0, the signal is LAOE. Line Add Bus Output Enable (LAOE). The Add Bus output enable signal is asserted high whenever the Line Add Bus is being driven which is co-coincident with the Line Add bus outputs coming out of tri-state. This pin is intended to control an external multiplexer when multiple TEMUX-84s are driving the Telecom Add bus during their individual tributaries. This same function is accomplished with the Add bus tristate drivers but increased tolerance to tributary configuration problems is possible with an external mux. This output is controlled via the LAOE bit in the TTMP Tributary Control registers when the egress VTPP is bypassed. When the egress VTPP is not bypassed or a TU-3 is being mapped, LAOE is high. Line Add Bus Tributary Payload Active (LATPL). The tributary payload active signal marks the bytes carrying the tributary payload. LATPL is high during each tributary payload byte on the LADATA[7:0] bus. LATPL will be low during transport overhead, path overhead, V1 bytes and V2 bytes. To indicate pointer adjustments, LATPL will be asserted appropriately during the V3 byte and following byte for the tributary. LAOE/LATPL is updated on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LADATA[0] LADATA[1] LADATA[2] LADATA[3] LADATA[4] LADATA[5] LADATA[6] LADATA[7]
Type
Pin Function No.
Output W14 Line Add Bus Data (LADATA[7:0]). The add bus data Tristate Y13 contains the SONET transmit payload data in byte AA13 serial format. All transport overhead bytes are set to AB13 00h. The phase relation of the SPE (VC) to the W13 transport frame is determined by the Add Bus AA12 composite timing signal LAC1J1V1 and is software W12 programmable to any valid pointer offset. LADATA[7] is W11 the most significant bit (corresponding to bit 1 of each serial word, the first bit to be transmitted). By default, LADATA[7:0] is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers. As options, LADATA[7:0] can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LADATA[7:0] is updated on the rising edge of LREFCLK.
LADP
Output AB14 Line Add Bus Data Parity (LADP). The Add Bus data parity signal carries the parity of the outgoing signals. Tristate The parity calculation encompasses the LADATA[7:0] bus and optionally the LAC1J1V1 and LAPL signals. LAC1J1V1 and LAPL can be included in the parity calculation by setting the INCLAC1J1V1 and INCLAPL register bits in the SONET/SDH Master Egress Configuration register high, respectively. Odd parity is selected by setting the LAOP register bit in the same register high and even parity is selected by setting the LAOP bit low. By default, LADP is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers. As options, LADP can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LADP is updated on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LAPL
Type
Pin Function No.
Output AA14 Line Add Bus Payload Active (LAPL). The Add Bus payload active signal identifies the payload bytes on Tristate LADATA[7:0]. LAPL is set high during path overhead and payload bytes and low during transport overhead bytes. By default, LAPL is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers. As options, LAPL can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LAPL is updated on the rising edge of LREFCLK.
LAV5
Output W15 Line Add Bus V5 Byte (LAV5). The outgoing tributary V5 byte signal marks the various tributary V5 bytes. Tristate LAV5 marks each tributary V5 byte on the LADATA[7:0] bus when high. By default, LAV5 is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers. As options, LAV5 can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LAV5 is updated on the rising edge of LREFCLK.
LDDATA[0] LDDATA[1] LDDATA[2] LDDATA[3] LDDATA[4] LDDATA[5] LDDATA[6] LDDATA[7]
Input
W5 AA6 AB5 Y3 Y6 AA5 AB4 AB3
Line Drop Bus Data (LDDATA[7:0]). The drop bus data contains the SONET/SDH receive payload data in byte serial format. LDDATA[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. LDDATA[7:0] is sampled on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LDDP
Type Input
Pin Function No. Y7 Line Drop Bus Data Parity (LDDP). The incoming data parity signal carries the parity of the incoming signals. The parity calculation encompasses the LDDATA[7:0] bus and optionally the LDC1J1V1 and LDPL signals. LDC1J1V1 and LDPL can be included in the parity calculation by setting the INCLDC1J1V1 and INCLDPL bits in the SONET/SDH Master Ingress Configuration register high, respectively. Odd parity is selected by setting the LDOP bit in the Master SONET/SDH Ingress Configuration register high and even parity is selected by setting the LDOP bit low. LDDP is sampled on the rising edge of LREFCLK.
LDC1J1V1
Input
AB6 Line Drop C1/J1 Frame Pulse (LDC1J1V1). The input C1/J1 frame pulse identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming SONET stream. LDC1J1V1 is set high while LDPL is low to mark the first C1 byte of the transport envelope frame on the LDDATA[7:0] bus. LDC1J1V1 is set high while LDPL is high to mark each J1 byte of the synchronous payload envelope(s) on the LDDATA[7:0] bus. LDC1J1V1 must be present at every occurrence of the first C1 and all J1 bytes. Optionally LDC1J1V1 indicates multiframe alignment when high during the first V1 bytes of each envelope. LDC1J1V1 is sampled on the rising edge of LREFCLK.
LDPL
Input
AB7 Line Drop Bus Payload Active (LDPL). The payload active signal identifies the bytes on LDDATA[7:0] that carry payload bytes. LDPL is set high during path overhead and payload bytes and low during transport overhead bytes. LDPL is set high during the H3 byte to indicate a negative pointer justification and low during the byte following H3 to indicate a positive pointer justification event. LDPL is sampled on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name LDV5
Type Input
Pin Function No. W6 Line Drop Bus V5 Byte (LDV5). The incoming tributary V5 byte signal marks the various tributary V5 bytes. LDV5 marks each tributary V5 byte on the LDDATA[7:0] bus when high. The LDV5 input is only used if the Ingress VTPP is bypassed (i.e. the IVTPPBYP bit of the SONET/SDH Master Ingress Configuration register is logic 1.) LDV5 is sampled on the rising edge of LREFCLK. Line Drop Bus Tributary Payload Active (LDTPL). The tributary payload active signal marks the bytes carrying the tributary payload which have been identified by an external payload processor. When this signal is available, the internal pointer processor can be bypassed. LDTPL is only respected for asynchronously mapped tributaries. LDTPL is high during each tributary payload byte on the LDDATA[7:0] bus. In floating mode, LDTPL contains valid data only for bytes in the VC3 or VC4 virtual containers, or the STS-1 SPE. It should be ignored for bytes in the transport overhead. In locked mode, LDTPL is low for transport overhead. LDTPL is sampled on the rising edge of LREFCLK.
LDTPL
Input
Y8
LDAIS
Input
AA8 Line Drop Bus Tributary Path Alarm Indication Signal (LDAIS). The active high tributary path alarm indication signal identifies tributaries on the incoming data stream LDDATA[7:0] that are in AIS state. When this signal is available, the internal pointer processor can be bypassed. LDAIS is invalid when LDTPL is low. LDAIS is only respected for asynchronously mapped tributaries. LDAIS is sampled on the rising edge of LREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name RADEASTCK
Type Input
Pin Function No. W7 Remote Alarm Port East Clock (RADEASTCK). The remote serial alarm port east clock provides timing for the east remote serial alarm port. It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADEASTFP and RADEAST are sampled on the rising edge of RADEASTCK.
RADEASTFP
Input
Y9
Remote Alarm Port East Frame Pulse (RADEASTFP). The remote serial alarm port east frame pulse is used to locate the alarm bits of the individual tributaries in the east remote serial alarm port. RADEASTFP is set high to mark the first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 carried in RADEAST. RADEASTFP must be set high to mark every occurrence of this bit. TEMUX-84 will not flywheel on RADEASTFP in order to accommodate a variety of RADEASTCK frequencies. RADEASTFP is sampled on the rising edge of RADEASTCK.
RADEAST
Input
AA9 Remote Alarm Port Data East (RADEAST). The remote serial alarm port east carries the tributary path BIP-2 error count, RDI status, and RFI status in the east remote serial alarm port. The first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 on RADEAST is marked by a high level on RADEASTFP. The status carried on RADEAST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0]. RADEAST is sampled on the rising edge of RADEASTCK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name RADWESTCK
Type Input
Pin Function No. W9 Remote Alarm Port West Clock (RADWESTCK). The remote serial alarm port west clock provides timing for the west remote serial alarm port. It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADWESTFP and RADWEST are sampled on the rising edge of RADWESTCK.
RADWESTFP
Input
Y10 Remote Alarm Port West Frame Pulse (RADWESTFP). The remote serial alarm port west frame pulse is used to locate the alarm bits of the individual tributaries in the west remote serial alarm port. RADWESTFP is set high to mark the first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 carried in RADWEST. RADWESTFP must be set high to mark every occurrence of this bit. TEMUX-84 will not flywheel on RADWESTFP in order to accommodate a variety of RADWESTCK frequencies. RADWESTFP is sampled on the rising edge of RADWESTCK.
RADWEST
Input
AA10 Remote Alarm Port Data West (RADWEST). The remote serial alarm port west carries the tributary path BIP-2 error count, RDI status, and RFI status in the west remote serial alarm port. The first BIP-2 error bit of tributary TU #1 in TUG2 #1 of TUG3 #1 on RADWEST is marked by a high level on RADWESTFP. The status carried on RADWEST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0]. RADWESTFP is sampled on the rising edge of RADWESTCK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name CLK52M
Type Input
Pin Function No. AB10 52 MHz Clock Reference (CLK52M). The 52Mhz clock reference is used to generate a gapped DS3 clock when demapping a DS3 from the SONET stream and also to generate a gapped DS3/E3 clock when receiving a DS3/E3 from the SBI bus interface. This clock has two nominal values.The first is a nominal 51.84 MHz 50% duty cycle clock. The second is a nominal 44.928 MHz 50% duty cycle clock. The expected frequency is determined by the FASTCLKFREQ bit of the SONET/SDH Master DS3 Clock Generation Control register. If E3 data rates are being supported, CLK52M must be 51.84MHz. F19 Common Transmit Clock (CTCLK). This input signal is used as a reference transmit tributary clock which can be used in egress Clock Master modes. CTCLK must be multiple of 8 kHz. The transmit clock is derived by the jitter attenuator PLL using CTCLK as a reference. The TEMUX may be configured to ignore the CTCLK input and lock to the data or one of the recovered Ingress clocks instead, RECVCLK1, RECVCLK2 and RECVCLK3. The receive tributary clock is automatically substituted for CTCLK if line loopback or looptiming is enabled.
Scaleable Bandwidth Interconnect Interface CTCLK Input
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SREFCLK
Type Input
Pin Function No. C10 System Reference Clock (SREFCLK). This system reference clock is a nominal 19.44 MHz +/-50ppm or 77.76 MHz +/-50ppm 50% duty cycle clock. This clock is common to both the add and drop sides of the SBI bus. SREFCLK must be active for all applications, except DS3/E3 framer only mode when the system interface is serial clock and data. When the SYSOPT register bits are binary 01 (H-MVIP interface), SREFCLK is required to be 19.44 MHz. This clock must be phase locked to LREFCLK and can be external connected to LREFCLK. When passing transparent virtual tributaries between the telecom bus and the SBI bus, SREFCLK must be the same frequency as LREFCLK (i.e. S77 = L77).
S77
Input
D10 The SBI 77.76 MHz select input determines the expected frequency of SREFCLK. If S77 is low, SREFCLK is expected to be 19.44 MHz. If S77 is high, SREFCLK is expected to be 77.76 MHz and data is driven and sampled every fourth cycle. This signal is a don't care when the SYSOPT register bits are binary 01 (H-MVIP interface). In this mode, SREFCLK is required to be 19.44 MHz. S77 is expected to be held static.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SDC1FP
Type I/O
Pin Function No. B3 SBI Drop C1 Frame Pulse (SDC1FP). The SDC1FP C1 frame pulse synchronizes devices interfacing to the Insert SBI bus. The frame pulse indicates SBI bus multiframe alignment which occurs every 500 mS, therefore this signal is pulsed every 9720 SREFCLK cycles (38880 cycles if S77 is high). This signal does not need to occur every SBI multiframe and is also used to indicate T1 and E1 multiframe alignment in synchronous SBI mode by pulsing at multiples of every 12 SBI multiframes (48 T1/E1 frames). In synchronous locked mode, as selected by the SYNCSBI context bit programmed through the RX-SBI-ELST Indirect Channel Data register, SDC1FP pulses every 116640 SREFCLK cycles (466560 cycles if S77 is high). If the SYNCSBI bit is logic 1 for at least one tributary, SDC1FP must indicate T1 and E1 multiframe alignment. The TEMUX-84 can be configured to generate this frame pulse. Only one device on the SBI bus should generate this signal. By default this signal is not enabled to generate the frame pulse. If a SDC1FP pulse is received at an unexpected cycle, the Drop bus with become high-impedance until two consecutive valid SDC1FP pulses occur. The system frame pulse is a single SREFCLK cycle long and is updated on the rising edge of SREFCLK. This signal must be held low if the SBI bus is not being used.
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Pin Name SAC1FP
Type Input
Pin Function No. B11 SBI Add C1 Frame Pulse (SAC1FP). The Extract C1 frame pulse synchronizes devices interfacing to the Extract SBI bus. The frame pulse indicates SBI bus multiframe alignment which occurs every 500 mS, therefore this signal is pulsed every 9720 SREFCLK cycles (38880 cycles if S77 is high). This signal does not need to occur every SBI multiframe.SAC1FP is sampled on the rising edge of SREFCLK. This signal must be held low if the SBI bus is not being used.
SADATA[0] SADATA[1] SADATA[2] SADATA[3] SADATA[4] SADATA[5] SADATA[6] SADATA[7] SADP
Input
A11 D12 B12 C12 D13 B13 C13 D14
System Add Bus Data (SADATA[7:0]). The System add data bus is a time division multiplexed bus which carries the E1, T1 and DS3 tributary data is byte serial format over the SBI bus structure. This device only monitors the add data bus during the timeslots assigned to this device. SADATA[7:0] is sampled on the rising edge of SREFCLK.
Input
A14 System Add Bus Data Parity (SADP). The system add bus signal carries the even or odd parity for the add bus signals SADATA[7:0], SAPL and SAV5. The TEMUX-84 monitors the add bus parity during all cycles when S77 is low and during the entire selected STM-1 when S77 is high. SADP is sampled on the rising edge of SREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SAPL
Type Input
Pin Function No. B14 System Add Bus Payload Active (SAPL). The add bus payload active signal indicates valid data within the SBI bus structure. This signal must be high during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to indicate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to indicate positive timing adjustments between the tributary rate and the fixed SBI bus structure. In the flexible bandwidth configuration, SAPL may only be asserted in response to a logic high on the SAJUST_REQ. SAPL shall be high an equal or less number of cycles than SAJUST_REQ. (Some applications require an exact one-to-one correspondence.) The TEMUX-84 only monitors the add bus payload active signal during the tributary timeslots assigned to this device. SAPL is sampled on the rising edge of SREFCLK.
SAV5
Input
C14 System Add Bus Payload Indicator (SAV5). The add bus payload indicator locates the position of the floating payloads for each tributary within the SBI bus structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure. All timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the SAPL signal. The TEMUX-84 only monitors the add bus payload indicator signal during the tributary timeslots assigned to this device. SAV5 is sampled on the rising edge of SREFCLK.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SAJUST_REQ
Type
Pin Function No. System Add Bus Justification Request (SAJUST_REQ). The justification request signals the Link Layer device to speed up, slow down or maintain the rate which it is sending data to the TEMUX-84. This is only used when the TEMUX-84 is the timing master for the tributary transmit direction. This active high signal indicates negative timing adjustments when asserted high during the V3 or H3 octet of the tributary. In response to this the Link Layer device sends an extra byte in the V3 or H3 octet of the next SBI bus multi-frame. Positive timing adjustments are requested by asserting justification request high during the octet following the V3 or H3 octet. The Link Layer device responds to this request by not sending an octet during the V3 or H3 octet of the next multi-frame. SAJUST_REQ has a different significance in the flexible bandwidth mode. In this mode, SAJUST_REQ is high for one SREFCLK cycle for each byte that can be accepted. A valid byte on SADATA[7:0] with an accompanying SAPL assertion is expected in response. The TEMUX-84 only drives the justification request signal during the tributary timeslots assigned to this device. When operating in 19.44 MHz mode (i.e. S77 low), SAJUST_REQ is aligned by the SAC1FP input. When operating in 77.76 MHz mode (i.e. S77 high), SAJUST_REQ's alignment is relative to the SDC1FP signal. SAJUST_REQ is updated on the rising edge of SREFCLK.
Output A2 Tristate
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SDDATA[0] SDDATA[1] SDDATA[2] SDDATA[3] SDDATA[4] SDDATA[5] SDDATA[6] SDDATA[7] SDDP
Type
Pin Function No. System Drop Bus Data (SDDATA[7:0]). The System drop data bus is a time division multiplexed bus which carries the E1, T1 and DS3 tributary data is byte serial format over the SBI bus structure. This device only drives the data bus during the timeslots assigned to this device. SDDATA[7:0] is updated on the rising edge of SREFCLK. System Drop Bus Data Parity (SDDP). The system drop bus signal carries the even or odd parity for the drop bus signals SDDATA[7:0], SDPL and SDV5. Whenever the TEMUX-84 drives the data bus, the parity is valid. SDDP is updated on the rising edge of SREFCLK. System Drop Bus Payload Active (SDPL). The payload active signal indicates valid data within the SBI bus structure. This signal is asserted during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI bus structure. In the flexible bandwidth configuration, SDPL is asserted for each byte as it becomes available. Therefore, SDPL may be high or low arbitrarily during any SREFCLK cycle. The TEMUX-84 only drives the payload active signal during the tributary timeslots assigned to this device. SDPL is updated on the rising edge of SREFCLK.
Output C5 Tristate A4 B5 C6 A5 B6 C7 D6 Output A6 Tristate
SDPL
Output A7 Tristate
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name SDV5
Type
Pin Function No. System Drop Bus Payload Indicator (SDV5). The payload indicator locates the position of the floating payloads for each tributary within the SBI bus structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure. All timing adjustments indicated by this signal are accompanied by appropriate adjustments in the SDPL signal. The TEMUX-84 only drives the payload Indicator signal during the tributary timeslots assigned to this device. SDV5 is updated on the rising edge of SREFCLK.
Output C8 Tristate
SBIACT
Output A3
SBI Output Active (SBIACT). The SBI Output Active indicator is high whenever the TEMUX-84 is driving the SBI drop bus signals. This signal is used by other TEMUX-84s or other SBI devices to detect SBI configuration problems by detecting other devices driving the SBI bus during the same tributary as the device listening to this signal. This output is updated on the rising edge or SREFCLK.
SBIDET[0] SBIDET[1]
Input
A15 SBI Bus Activity Detection (SBIDET[1:0]). The SBI B15 bus activity detect input detects tributary collisions between devices sharing the same SBI bus. Each SBI device driving the bus also drives an SBI active signal (SBIACT). This pair of activity detection inputs monitors the active signals from two other SBI devices. When unused this signal should be connected to ground. These inputs only have effect when the SBI bus is configured for 19.44MHz (i.e. S77 is low). A collision is detected when either of SBIDET[1:0] signals are active concurrently with this device driving SBIACT. When collisions occur the SBI drivers are disabled and an interrupt is generated to signal the collision.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name
Type
Pin Function No.
Microprocessor Interface INTB Output T21 Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is OD detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source. Input AA15 Active Low Chip Select (CSB). This signal is low during TEMUX-84 register accesses. The CSB input has an integral pull up resistor. RDB Input W17 Active Low Read Enable (RDB). This signal is low during TEMUX-84 register read accesses. The TEMUX-84 drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. AB16 Active Low Write Strobe (WRB). This signal is low during a TEMUX-84 register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. U22 Bidirectional Data Bus (D[7:0]). This bus provides T20 TEMUX-84 register read and write accesses. V19 U21 U20 W22 Y22 Y21
CSB
WRB
Input
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
I/O
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] RSTB
Type Input
Pin Function No. AB22 Address Bus (A[12:0]). This bus selects specific AA21 registers during TEMUX-84 register accesses. Y19 Signal A[12] selects between normal mode and test AA20 mode register access. A[12] has an integral pull down AA19 resistor. Tie A[12] directly to ground unless access to AB20 bit HIZIO in test register 0x1000 is required. AA18 W19 AB18 AA17 W18 Y16 AA16 W20 Active Low Reset (RSTB). This signal provides an asynchronous TEMUX-84 reset. RSTB is a Schmitt triggered input with an integral pull up resistor. AA22 Address Latch Enable (ALE). This signal is active high and latches the address bus A[12:0] when low. When ALE is high, the internal address latches are transparent. It allows the TEMUX-84 to interface to a multiplexed address/data bus. The ALE input has an integral pull up resistor. B1 Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. Test Data Input (TDI). This signal carries test data into the TEMUX-84 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor.
Input
ALE
Input
JTAG Interface TCK Input
TMS
Input
D2
TDI
Input
E3
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name TDO
Type
Pin Function No. Test Data Output (TDO). This signal carries test data out of the TEMUX-84 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress. Active low Test Reset (TRSTB). This signal provides an asynchronous TEMUX-84 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB must be connected to the RSTB input.
Output D1
TRSTB
Input
C1
Power and Ground Pins VDD3.3[19] VDD3.3[18] VDD3.3[17] VDD3.3[16] VDD3.3[15] VDD3.3[14] VDD3.3[13] VDD3.3[12] VDD3.3[11] VDD3.3[10] VDD3.3[9] VDD3.3[8] VDD3.3[7] VDD3.3[6] VDD3.3[5] VDD3.3[4] VDD3.3[3] VDD3.3[2] VDD3.3[1] Power A18 Power (VDD3.3[19:1]). The VDD3.3[19:1] pins should A22 be connected to a well decoupled +3.3V DC power AB17 supply. D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name VDD1.8[19] VDD1.8[18] VDD1.8[17] VDD1.8[16] VDD1.8[15] VDD1.8[14] VDD1.8[13] VDD1.8[12] VDD1.8[11] VDD1.8[10] VDD1.8[9] VDD1.8[8] VDD1.8[7] VDD1.8[6] VDD1.8[5] VDD1.8[4] VDD1.8[3] VDD1.8[2] VDD1.8[1]
Type
Pin Function No.
Power C2 Power (VDD1.8[19:1]). The VDD1.8[19:1] pins should D3 be connected to a well-decoupled +1.8V DC power J2 supply. R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name VSS[69] VSS[68] VSS[67] VSS[66] VSS[65] VSS[64] VSS[63] VSS[62] VSS[61] VSS[60] VSS[59] VSS[58] VSS[57] VSS[56] VSS[55] VSS[54] VSS[53] VSS[52] VSS[51] VSS[50] VSS[49] VSS[48] VSS[47] VSS[46] VSS[45] VSS[44] VSS[43] VSS[42] VSS[41] VSS[40] VSS[39] VSS[38] VSS[37] VSS[36] VSS[35] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30]
Type
Pin Function No.
Ground C4 Ground (VSS3.3[69:1]). The VSS[69:1] pins should A12 be connected to GND. AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin Name VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4] VSS[3] VSS[2] VSS[1] Unconnected Unconnected
Type
Pin Function No. L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17 A1 These balls have no internal connections. They may B2 be left floating or tied to a static logic level. L4 P4 T19
Notes on Pin Descriptions: 1. All TEMUX-84 inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
2. All TEMUX-84 outputs and bi-directionals have at least 2 mA drive capability. The bidirectional data bus outputs, D[7:0], have 4 mA drive capability. The outputs TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, LAOE/LATPL, RECVCLK1, RECVCLK2, RECVCLK3, CASID[21:1], CCSID, TS0ID, TDO and INTB have 4 mA drive capability. The SBI outputs and telecom bus outputs, SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SAC1FP, LAV5, LAC1J1V1, LADATA[7:0], LADP and LAPL, have 8mA drive capability. The bidirectional SBI signal SDC1FP has 8mA drive capability. MVID[21:1] have 8mA drive capability. 3. Inputs CSB, RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 4. Input A[12] has an internal pull-down resistor. 5. All unused inputs should be connected to GROUND. 6. Power to the VDD3.3 pins should be applied before power to the VDD1.8 pins is applied. Similarly, power to the VDD1.8 pins should be removed before power to the VDD3.3 pins is removed.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9
FUNCTIONAL DESCRIPTION The TEMUX-84 supports a total throughput of 155.52Mbit/s (including overhead) in both transmit (a.k.a. egress) and receive (a.k.a. ingress) directions. The bandwidth is divided into three approximately equal data streams, each independently configured relative to the others. Configurations include, but are not limited to: * 28 1.544Mbit/s or 21 2.048Mbit/s tributaries multiplexed into a DS3 or mapped into a SONET/SDH structure. The tributaries may be framed T1s, framed E1s, transparent virtual tributaries (TVTs) or clear channel. A single 44.736Mbit/s or 34.386Mbit/s stream. It may be a T3, E3 or clear channel. The 44.736Mbit/s data stream may be mapped into a SONET/SDH structure.
*
9.1
Transparent Virtual Tributaries Transparent virtual tributaries (TVTs) are supported when performing VT1.5/TU11 or VT2/TU12 mapping into the Telecom Bus and the SBI Bus is being used. Conceptually, a TVT is passed straight from the Telecom Bus to the SBI Bus (and visa versa) with no knowledge of the mapping protocol or T1/E1 framing. On the SBI Add Bus there are two methods of indicating transmit pointers. If the ETVTPTRDIS or EPTRBYP bit is logic 1, the SAV5 input must indicate the location of the V5 byte and the V1/V2 bytes need not be valid at the SBI Add Bus. If both ETVTPTRDIS and EPTRBYP bit are logic 0, the V1/V2 bytes at the SBI Add Bus must contain a pointer to the V5 byte. The Egress VTPPs accommodate the arbitrary alignment of the SBI and Telecom Add buses by encoding a new V1/V2 value and generating a LAV5 output pulse to match. The Telecom bus may be formatted as AU3s or as an AU4; the VTPPs will translate the AU3s to the AU4 format of the SBI bus. A TVT presented by the Telecom Drop bus must contain a valid V1/V2 pointer. The V1/V2 will be modified in the process of mapping the TVT into the SBI Drop Bus, which by definition has a SPE alignment equivalent to a pointer of 522 decimal. Tributary and path pointer justifications on the Telecom Drop Bus will result in corresponding rate justifications at the SBI Drop Bus as indicated by the SDPL signal. The SDV5 output will always indicate the V5 byte location.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
The Clock and Frame Synchronization Constraints section indicates constraints on bus alignments imposed by TVT support. 9.2 Transmultiplexing Transmultiplexing ("transmux") is the operating mode that enables 1.544 Mb/s and 2.048 Mb/s unstructured tributaries to be exchanged between the SONET/SDH Telecom Bus and the DS3 line interface. It is enabled on a perSPE/DS3 basis by setting an SPE Configuration register's OPMODE_SPEx[2:0] bits to 010 and it's LINEOPT_SPEx[1:0] bits to 00. The system interface is unused in this mode. The TEMUX-84 will receive a channelized DS3 stream from the serial clock and data inputs. It will frame up to the DS3 and de-multiplex the individual 1.544 Mb/s or 2.048 Mb/s tributaries. The tributaries are jitter attenuated, bit asynchronously mapped into VT1.5/TU11s or VT2/TU12s and presented on the Telecom Add bus. Byte synchronous mapping is not an option in transmux mode. In the reverse direction, VT1.5/TU11s or VT2/TU12s are bit asynchronously demapped from the Telecom Drop bus. The 1.544 Mb/s or 2.048 Mb/s tributaries are jitter attenuated and multiplexed into a DS3, which is presented on the serial clock and data outputs. The correspondence between the DS3 tributaries and the SONET/SDH VT/TUs is provided in the Tributary Indexing section. Performance monitoring as documented in the T1/E1 Performance Monitoring section can be performed on the tributaries. In addition, HDLC channels and PRBS patterns may be monitored. With the exception of unframed PRBS reception, the performance monitoring assumes the tributaries are standard T1 or E1 data streams. On a per-tributary basis, the TXPMON context bit programmed through the RJAT Indirect Channel Data Register selects either the SONET/SDH mapper transmit or DS3 transmit tributary for performance monitoring. 9.3 T1 Framing T1 framing can be performed on up to three sets of 28 tributaries. Each set of tributaries may be multiplexed into a DS3 or mapped into a SPE via VT1.5s/TU11s. The T1 framing function searches for the framing bit pattern in the standard Superframe (SF), SLCO96 or Extended Superframe (ESF) framing formats.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
When searching for frame each of the 193 (SF or SLCO96) or each of the 772 (ESF) framing bit candidates is simultaneously examined. The time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1 framer will determine frame alignment within 4.4ms 99 times out of 100. For SLC(R)96 format, the T1 framer will determine frame alignment within 13ms. For ESF format, the T1 framer will determine frame alignment within 15 ms 99 times out of 100. Once the T1 framer has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The performance data is accumulated for each tributary. The T1 framer also detects out-of-frame, based on a selectable ratio of framing bit errors. For ESF, out-of-frame declaration is based strictly on Frame Alignment Signal (F1-F6) bit errors; a new frame search is never initiated upon excessive CRC-6 errors. The framing function can also be disabled to allow reception of unframed data. 9.3.1 Inband Code Detection The framer detects the presence of either of two programmable inband loopback activate and deactivate code sequences in either framed or unframed data streams (whether data stream is framed or unframed is not programmable) . The loopback codes will be detected in the presence of a mean bit error rate of up to 10-2. When the inband code is framed, the framing bits overwrite the code bits, thus appearing to the receiver as a 2.6x10-3 BER (which is within the tolerable BER of 10-2). Code indication is provided on the active high loopback activate (LBA) and loopback deactivate (LBD) status bits. Changes in these status bits result in the setting of corresponding interrupt status bits, LBAI and LBDI respectively, and can also be configured to result in the setting of a maskable interrupt indication. The inband loopback activate condition consists of a repetition of the programmed activate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). The inband loopback deactivate condition consists of a repetition of the programmed deactivate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). Programmed codes can be from three to eight bits in length.
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
The code sequence detection and timing is compatible with the specifications defined in T1.403, TR-TSY-000312, and TR-TSY-000303. 9.3.2 T1 Bit Oriented Code Detection The presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format is detected, as defined in ANSI th T1.403 and in TR-TSY-000194. The 64 code (111111) is similar to the HDLC flag sequence and is used to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). The receiver declares a received code valid if it has been observed for two consecutive times The code is declared removed if two code sequences containing code values different from the detected code are received two consecutive times. Valid BOC are indicated through the BOCI status bit The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones). 9.3.3 T1 Alarm Integration The presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, SLCO96 or ESF formats is detected and integrated in accordance with the specifications defined in ANSI T1.403 and TR-TSY-000191. The presence of Yellow alarm is declared when the Yellow pattern has been received for 400 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 400 ms ( 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out-offrame condition and all-ones in the PCM data stream have been present for 2.55 sec (40 ms); the AIS alarm is removed when the AIS condition has been absent for 16.6 sec (500 ms). CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate. 9.3.3.1 Customer Interface Alarms The RAI-CI and AIS-CI alarms defined in T1.403 are detected reliably.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
By definition, RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of 00000000 11111111 (right-to-left) with 90 ms of 00111110 11111111. RAI-CI is declared when a bit oriented code of "00111110 11111111" is validated (i.e. two consecutive patterns) while RAI (a.k.a. Yellow alarm) is declared. RAI-CI is cleared upon deassertion of RAI or upon 28 consecutive 40ms intervals without validation of "00111110 11111111". By definition, AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones. AIS-CI is an unframed pattern, so it is defined for all framing formats. AIS-CI is declared between 1.40 and 2.56 seconds after initiation of the AIS-CI signal and is deasserted 16.6 seconds after it ceases. 9.4 E1 Framing E1 framing can be performed on up to three sets of 21 tributaries. Each set of tributaries may be multiplexed into a DS3 according to the ITU-T Rec. G.747 standard or mapped into a SPE via VT2s/TU-12s. The E1 framing function searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream. Once basic (or FAS) frame alignment has been found, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors, which are accumulated in a framing bit error counter dedicated to each tributary. Once CRC multiframe alignment has been found, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors and CRC-4 errors, which are accumulated in a CRC error counter dedicated to each tributary. Once CAS multiframe alignment has been found, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1 framer also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software, by excessive CRC errors, or when CRC multiframe alignment is not found within 400 ms. The E1 framer extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
16 of frame 0 of the CAS multiframe). Moreover, the framer also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe. The E1 framer identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe). Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 4 (provided the RAIC bit is logic 1) and 3 consecutive occurrences, respectively, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms. An interrupt may be generated to signal a change in the state of any status bits (INF, INSMF, INCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe. Basic Frame Alignment Procedure The E1 framer searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2. The algorithm finds frame alignment by using the following sequence: 1. Search for the presence of the correct 7-bit FAS (`0011011'); 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (NFAS) TS 0 byte is a logic 1; 3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame. If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS.
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The algorithm provides robust framing operation even in the presence of random bit errors; the algorithm provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10-3 bit error rate and no mimic patterns. Once frame alignment is found, the INF context bit is set to logic 1, a change of frame alignment is indicated (if it occurred), and the frame alignment signal is monitored for errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and the debounced value of the Remote Alarm bit (bit 3 of NFAS frames) is reported. Loss of frame alignment is declared if 3 consecutive FASs have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. The E1 framer can be forced to initiate a basic frame search at any time when any of the following conditions are met: * * * the software re-frame bit, REFR, in the T1/E1 Framer Indirect Channel Data registers is set to logic 1; the CRC Frame Find Block is unable to find CRC multiframe alignment; or the CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame under that condition. CRC Multiframe Alignment Procedure The E1 framer searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms Once CRC multiframe alignment is found, the INCMF register bit is set to logic 1, and the E1 framer monitors the multiframe alignment signal (MFAS), indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1 framer declares loss of CRC multiframe alignment if basic frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern. Under the CRC-to-non-CRC interworking algorithm, if the E1 framer can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms,
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the distant end is assumed to be a non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 9. Figure 9 CRC Multiframe Alignment Algorithm
O ut of Fram e
3 consecutiv e FAS or NF AS errors; m anual refram e; or excessiv e C RC errors
FAS_Find_1
NFAS not found next fram e
FAS_Find_1_Par
FAS found NFAS not found next fram e
FAS found
NFAS_Find
NFAS found next fram e FAS not found next fram e
NFAS_Find_Par
NFAS found next fram e FAS not found next fram e
FAS_Find_2
FAS found next fram e 8m s expire
Start 400m s tim er and 8m s tim er
FAS_Find_2_Par
FAS found next fram e
Start 8m s tim er
BFA
CRC MFA
8m s expire and NOT(400m s expire)
Reset BFA to m ost recently found alignm ent
BFA_Par
400m s expire
CR CMFA_Par
CRC to CRC Interworking
CR CM FA_Par (Optional setting)
CRC to non-CRC Interworking
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Table 1 E1 framer Framing States State FAS_Find_1 NFAS_Find FAS_Find_2 BFA CRC to CRC Interworking FAS_Find_1_Par NFAS_Find_Par FAS_Find_2_Par BFA_Par CRC to non-CRC Interworking Out of Frame Yes Yes Yes No No No No No No No Out of Offline Frame No No No No No Yes Yes Yes No No
The states of the primary basic framer and the parallel/offline framer in the E1 framer block at each stage of the CRC multiframe alignment algorithm are shown in Table 1. From an out of frame state, the E1 framer attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared. If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline
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search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment). Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1 framer stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1 framer may be optionally set to either halt searching for CRC multiframe altogether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct. AIS Detection When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD context bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0. Signaling Frame Alignment Once the basic frame alignment has been found, the E1 framer searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct CAS alignment pattern, namely four zeros ("0000") in the first four bit positions of timeslot 16. Once signaling multiframe alignment has been found, the E1 framer sets the INSMF context bit of the tributary to logic 1, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). This E1 framer also indicates the reception of TS 16 AIS when time slot 16 has been received with three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS status is cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR when the signaling multiframe signal is found.
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The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost. National Bit Extraction The E1 framer extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt. This E1 framer also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are zeros. Upon reception of this Link ID signal, the V52LINKV context bit is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones. E1 Alarm Integration The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms ( 6 ms). The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1 framer counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate. The Red alarm algorithm monitors occurrences of out of frame (OOF) over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs.
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The E1 framer can also be disabled to allow reception of unframed data. 9.5 T1/E1 Performance Monitoring CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events are accumulated with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the counter values are transferred into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, the OVR context bit is asserted to indicate data loss. A bit error event (BEE) is defined as an F-bit error for SF and SLCO96 framing format or a CRC-6 error for ESF framing format. A framing bit error (FER) is defined as an Fs or Ft error for SF and SLCO96 and an Fe error for ESF framing format. The transfer clock within the TEMUX-84 chip is generated precisely once per second (i.e. 19440000 SREFCLK cycles) if the AUTOUPDATE bit of the T1/E1 Framer Configuration and Status register is logic 1 or by writing to the Global PMON Update register with the FRMR bit set. Coincident with the counter transfer, a Performance Report Message (PRM) is transmitted for each T1 tributary for which the PRMEN context bit is logic 1. 9.6 T1/E1 HDLC Receiver The HDLC Receiver is a microprocessor peripheral used to receive HDLC frames on the 4 kHz ESF facility data link or the E1 Sa-bit data link. A data link can also be extracted from any sub-set of bits within a single DS0. The HDLC Receiver detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). Received data is placed into a 127-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The RHDL Indirect Channel Data Registers contain bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence end of
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message bytes written into the FIFO. The RHDL Indirect Channel Data Registers also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the RHDL Indirect Channel Data Registers indicates the FCS status and if the packet contained a non-integer number of bytes. 9.7 T1/E1 Elastic Store (ELST) Frame slip buffers exist in both the ingress and egress directions. In the ingress direction, the Elastic Store (ELST) synchronizes ingress frames to the common ingress H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in H-MVIP modes. When using the SBI bus, the elastic store is required in locked or slave mode. In the egress direction, the Elastic Store is required in H-VIP mode or in SBI slave or locked modes when the transmit data is loop timed or referenced to one of the recovered clocks (RECVCLK1, RECVCLK2, RECVCLK3). The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane/transmit clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent frame is deleted. If the average frequency of the incoming data is less than the average frequency of the backplane/transmit clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous frame is repeated. A slip operation is always performed on a frame boundary. When the ingress timing is recovered from the receive data, the ingress elastic store can be bypassed to eliminate the 2 frame delay. To allow for the extraction of signaling information in the data channels, superframe identification is also passed through the ELST. For payload conditioning, the ingress ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the ELST is reset.
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9.8
T1/E1 Signaling Extraction Channel associated signaling (CAS) is extracted from an E1 signaling multiframe or from ESF, SLCO96 and SF T1 formats. In T1 mode, signaling bit are extracted from the received data streams for ESF, SLCO96 and SF framing formats. The signaling states are optionally debounced and serialized onto the CASID[x] H-MVIP outputs or CAS bits within the SBI Bus structure. Debouncing is performed on the entire signaling state. This CASID[x] output is channel aligned with the MVID[x] output, and the signaling bits are repeated for the entire superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in ESF framing format. In SF and SLCO96 format, bits 5 and 6 contain the A and B bits from every second superfame and bits 7 and 8 contain the A and B bits from the alternate superframes. The four bits are updated every 24 frames and are debounced collectively. Three superframes for ESF and six superframes for SLCO96 and SF worth of signal are buffered to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 ESF superframes or 4 SF/SLCO96 superframes before appearing on the serial output stream. One superframe or signaling-multiframe of signal freezing is provided on the occurrence of slips. When a slip event occurs, output signaling for the entire superframe in which the slip occurred is frozen; the signaling is unfrozen when the next slip-free superframe occurs. Control over timeslot signaling bit fixing and signaling debounce is provided on a per-timeslot basis. An interrupt is provided to indicate a change of signaling state on a per channel basis.
9.9
T1/E1 Receive Per-Channel Control Data and signaling trunk conditioning may be applied on the ingress stream on a per-channel basis. Also provided is per-channel control of data inversion and the detection and generation of pseudo-random patterns. These operations occur on
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the data after its passage through frame slip buffer, so that data and signaling conditioning may overwrite the trouble code. 9.10 T1 Transmitter The T1 transmitter generates the 1.544 Mbit/s T1 data streams according to SF, SLCO96 or ESF frame formats. The transmitter provides per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones density control. Context bits provide per-channel control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state by the Master Trunk Conditioning (MTRK) context bit. The transmitter may source pseudo-random bit sequences (PRBS) in a selected subset of channels, while simultaneously monitoring the data from the system interface for PRBS errors. A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC messages. If the T1_FDL_DIS context bit is logic 1, the data link is sourced from the F-bit position of the H-MVIP or SBI interface. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS, Yellow, AIS-CI and RAI-CI (ESF only) alarm signals for all formats. If the AUTOUPDATE bit of the T1/E1 Framer Configuration and Status register is logic 1, the T1 transmitter automatically sends an ANSI T1.403-formatted performance report on the T1 facility data link once per second. The F-bit may be passed transparently from either the H-MVIP or SBI interface. To support alignment of the robbed bit signaling to the F-bits, the C8MVFPB input may be redefined as a superframe alignment pulse. The transmitter can be disabled for framing via the FDIS context bit. 9.10.1 SLCO96 SLCO96 is partially supported. The F-bits must be sourced from the system interface. To pass the F-bits transparently, the FDIS context bit must be set. Also, a superframe alignment must be provided to ensure the robbed-bit signaling is inserted in the correct frames relative to the F-bits. To ensure the
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framing is not corrupted, the timing must be configured to avoid controlled frame slips. When using the SBI interface, it is recommended the transmit frame slip buffer be bypassed and that the transmit clock be locked to the data stream (i.e. TJAT LOOPT and REFSEL context bits logic 0). With an H-MVIP interface, the transmit elastic store cannot be bypassed, so the transmit clock must be locked to CTCLK which must be presented a clock that is locked to CMV8MCLK. 9.10.2 T1 Bit Oriented Code Generation 63 of the possible 64 bit oriented codes may be transmitted in the Facility Data Link (FDL) channel in ESF framing format, as defined in ANSI T1.403-1995. When transmission is disabled the FDL is set to all ones. Bit oriented codes are transmitted on the T1 Facility Data Link as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. When driving the T1 facility data link the transmitted bit oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to be transmitted is programmed by writing to the BOC code context bits where it is held until the latest code has been transmitted at least 10 times. 9.11 E1 Transmitter The E1 transmitter generates a 2048 kbit/s data streams according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation. The E1 transmitter provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning (MTRK) context bit. The transmitter may source pseudo-random bit sequences (PRBS) in a selected sub-set of channels, while simultaneously monitoring the data from the system interface for PRBS errors. Common Channel Signaling (CCS) is supported in time slots 15, 16 and 31. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm (RAI) and remote multiframe alarm signals.
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The National Use bits (Sa-bits) can be sourced from the National Bits Codeword context bits as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controller, or may be passed transparently from the MVED[x] inputs. 9.12 T1/E1 HDLC Transmitters The HDLC transmitter provides a serial data link for the 4 kHz ESF facility data link or E1 Sa-bit data link. The data link may also be presented in any sub-set of bits within a selected DS0. The HDLC transmitter is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the HDLC transmitter data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the HDLC transmitter continuously transmits the flag sequence (01111110) until data is ready to be transmitted. The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The HDLC transmitter then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. A second mechanism transmits data when the FIFO depth has reached a user configured upper threshold. The HDLC transmitter will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences.
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Abort characters can be continuously transmitted at any time by setting the ABT bit. During packet transmission, an underrun situation can occur if data is not written before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt. 9.13 T1/E1 Receive and Transmit Digital Jitter Attenuators The TEMUX-84 contains two separate jitter attenuators, one between the receive demultiplexed or demapped T1 or E1 link and the ingress interface and the other between the egress interface and the transmit T1 or E1 link to be multiplexed into DS3 or mapped into SONET/SDH. Each jitter attenuator receives jittered data and stores the stream in a FIFO timed to the associated clock. The jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock. In the receive jitter attenuator, the jitter attenuated clock is referenced to the demultiplexed or demapped tributary receive clock. In the transmit jitter attenuator, the jitter attenuated transmit tributary clock feeding the M13 multiplexer or SONET/SDH mapper may be referenced to either the data stream, the CTCLK primary input, or the tributary receive clock. Jitter Characteristics The jitter attenuators provide excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. In T1 mode, each jitter attenuator can accommodate up to 48 UIpp of input jitter at jitter frequencies above 4 Hz. For jitter frequencies below 4 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In E1 mode each jitter attenuator can accommodate up to 48 UIpp of input jitter at jitter frequencies above 5 Hz. For jitter frequencies below 5 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In most applications, each jitter attenuator will limit jitter tolerance at lower jitter frequencies only. The jitter attenuator meet the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and ITUT Recommendation G.823, and thus allow compliance with these standards and the other less stringent jitter tolerance standards cited in the references. The jitter attenuators exhibit negligible jitter gain for jitter frequencies below 3.4 Hz, and attenuates jitter at frequencies above 3.4 Hz by 20 dB per decade in T1 mode. It exhibits negligible jitter gain for jitter frequencies below 5 Hz, and attenuates jitter at frequencies above 5 Hz by 20 dB per decade in E1 mode. In most applications the jitter attenuators will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through the jitter attenuators. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be
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dominated by the waiting time jitter introduced by the multiplexing into DS3 or mapping into SBI or SONET/SDH. The jitter attenuator allows the implied T1 jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met. The jitter attenuator meets the E1 jitter attenuation requirements of the ITU-T Recommendations G.737, G.738, G.739 and G.742. Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For T1 modes the jitter attenuator input jitter tolerance is 48 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 278 Hz. For E1 modes the input jitter tolerance is 48 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 369 Hz. Figure 10 Jitter Tolerance T1 Modes
100 48 28 10 Jitter Amplitude (UI pp) Minimum Jitter Tolerance
62411Min 1.0 acceptable 0.4 unacceptable 0.1
0.01 1
4.9
10
100 300 1k Jitter Frequency (Hz)
10k
100k
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Figure 11 Jitter Tolerance E1 Modes
100 40 Minimum Jitter Tolerance 48
10 Jitter Amplitude (UI pp)
ITU-T G.823 Min 1.5 1.0 acceptable unacceptable 0.1 0.2
0.01 1
10
20
100 1k Jitter Frequency (Hz)
2.4k
10k18k
100k
Jitter Transfer The output jitter in T1 mode for jitter frequencies from 0 to 3.4 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 3.4 Hz are attenuated at a level of 20 dB per decade, as shown in Figure 12.
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Figure 12 Jitter Transfer T1 Modes
0
-10
Jitter Attenuator Response 43802 Max
Jitter Gain (dB)
-20 62411 Max
-30
62411 Min -40
-50 1
3.4
10
20
350 100 1k Jitter Frequency (Hz)
10k
100k
The output jitter in E1 mode for jitter frequencies from 0 to 5.0 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 2.5 Hz are attenuated at a level of 20 dB per decade, as shown in Figure 13.
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Figure 13 Jitter Transfer E1 Modes
0
-10
G.737, G.738, G.739, G.742 Max
unacceptable Jitter Gain (dB) -20 acceptable
-30
Jitter Attenuator Response
-40
-50 1
5
10
40
400 100 1k Jitter Frequency (Hz)
10k
100k
Frequency Range The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (48 UIpp) and maximum SREFCLK frequency offset ( 50 ppm). The tracking range is 1.544 MHz 997 Hz with no jitter or SREFCLK frequency offset. The guaranteed linear operating range for the jittered input clock is 2.048 MHz 266 Hz with worst case jitter (48 UIpp) and maximum SREFCLK frequency offset ( 50 ppm). The tracking range is 2.048 MHz 999 Hz with no jitter or SREFCLK frequency offset.
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9.14 T1/E1 Pseudo Random Binary Sequence Generation and Detection (PRBS) The Pseudo Random Binary Sequence Generator/Detector (PRBS) is a software selectable PRBS generator and checker for 27-1, 211-1, 215-1 or 220-1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated and monitored in both the transmit or receive directions for all T1 and E1 links simultaneously. The generator is capable of inserting single bit errors under microprocessor control. The detector auto-synchronizes to the expected PRBS pattern and accumulates the total number of bit errors in a 16-bit counter. The error count accumulates over the interval defined by writes to the Global PMON Update register. When a transfer is triggered, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available until the next transfer. In addition to the basic PRBS generators and receivers associated with each T1/E1 link, six full-featured pattern generator/detector pairs are available for association with any software selectable link. Any subset of bits within a frame (except the T1 F-bit) may be programmed to carry either a pseudo-random or fixed pattern. The six generators can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. It also can generate the four DDS codes specified by Bellcore GR-819CORE. In addition, the pattern generator can insert single bit errors or a bit error rate between 10-1 to 10-7. The six receivers can be programmed to check for the generated pseudo random pattern. The receivers can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. If a repetitive pattern is selected, the receiver will synchronize to any bit sequence that repeats with the programmed periodicity. A bit error accumulates when a bit disagrees with the original bit sequence synchronized to. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When a transfer is triggered, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next transfer.
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9.15 DS3 Framer (DS3-FRMR) Three instances of the DS3 Framer are independently programmed. From each the framed data is presented on RDATO[x], mapped into the SBI bus or may be demultiplexed to 28 DS1s or 21 E1s (ITU-T Rec. G.747). The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications. The DS3-FRMR decodes a B3ZS-encoded signal and provides indications of line code violations. The B3ZS decoding algorithm and the LCV definition can be independently chosen through software. A loss of signal (LOS) defect is also detected for B3ZS encoded streams. LOS is declared when inputs RPOS and RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when the ones density on RPOS and/or RNEG is greater than 33% for 175 1 RCLK cycles. The framing algorithm examines five F-bit candidates simultaneously. When at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. When a single F-bit candidate remains in a set, the first bit in the supposed M-subframe is examined for the M-frame alignment signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing is declared, and out-of-frame is removed, if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. During the examination of the M-bits, the X-bits and P-bits are ignored. The algorithm gives a maximum average reframe time of 1.5 ms. While the DS3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled by the MBDIS bit in the DS3 Framer Configuration register. The 3 out of 8 consecutive F-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive F-bits ratio. Either out-of-frame criteria allows an out-offrame defect to be detected quickly when the M-subframe alignment patterns or, optionally, when the M-frame alignment pattern is lost. Also while in-frame, line code violations, M-bit or F-bit framing bit errors, and Pbit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and far end block errors are indicated. These error indications, as
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well as the line code violation and excessive zeros indication, are accumulated over 1 second intervals with the Performance Monitor (DS3-PMON). Note that the framer is an off-line framer, indicating both OOF and COFA events. Even if an OOF is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the DS3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" M-frame intervals. For the RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE) while valid frame alignment is maintained. This discrepancy threshold ensures the detection algorithms operate in the presence of a 10-3 bit error rate. For AIS, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and the Cbits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). Each "valid" Mframe causes an associated integration counter to increment; "invalid" M-frames cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). RED, AIS, or IDLE are removed when the respective counter decrements to 0. DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is deasserted. Valid X-bits are extracted by the DS3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status remains in its previous state. The extracted FERF status is buffered for 2 Mframes before being reported within the DS3 FRMR Status register. This buffer ensures a better than 99.99% chance of freezing the FERF status on a correct value during the occurrence of an out of frame.
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When the C-bit parity application is enabled, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. Codes in the FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC messages in the Path Maintenance Data Link are received by the Data Link Receiver (RDLC). The DS3-FRMR can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error. The DS3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS3-FRMR. Access to these registers is via a generic microprocessor bus. 9.16 DS3 Bit Oriented Code Detection The presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format is detected, as defined in ANSI T1.403 and in TR-TSY-000194 or in the DS3 C-bit parity far-end alarm and Th control (FEAC) channel. The 64 code (111111) is similar to the HDLC flag sequence and is used to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel or FEAC channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10 times. The receiver can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC context bit. The code is declared removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods. Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones). 9.17 DS3/E3 HDLC Receiver (RDLC) The RDLC is a microprocessor peripheral used to receive HDLC frames on the DS3 C-bit parity Path Maintenance Data Link, E3 G.832 Network Operator byte,
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E3 G.832 General Purpose Communications Channel or E3 G.751 National Use bit. The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes. 9.18 DS3/E3 Performance Monitor Accumulator (DS3/E3-PMON) The Performance Monitor (PMON) Block interfaces directly with the DS3 Framer (DS3-FRMR) and E3 Framer. Saturating counters are used to accumulate: * * * * * * line code violation (LCV) events parity error (PERR) events path parity error (CPERR) events far end block error (FEBE) events excess zeros (EXZS) framing bit error (FERR) events Due to the off-line nature of the DS3 and E3 Framers, PMON continues to accumulate performance metrics even while the framer has declared OOF.
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When an accumulation interval is signaled by a write to the PMON register address space or to the Global PMON Update register, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed. When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval. Whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. 9.19 DS3 Transmitter (DS3-TRAN) Three DS3 transmitters are instantiated. Each may be programmed to provide framing for unchannelized data from TDATI[x] or the SBI bus, or framing for multiplexed T1s or E1s (ITU-T Rec. G.747). The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats. Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the DS3-FRMR. A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted. When enabled for C-bit parity operation, the FEAC channel is sourced by the bitoriented code transmitter. The path maintenance data link messages are sourced by the TDPR data link transmitter. The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros.
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9.19.1 DS3 Bit Oriented Code Generation 63 of the possible 64 bit oriented codes may be transmitted in the DS3 C-bit parity Far-End Alarm and Control (FEAC) channel. The 64th code (111111) is similar to the HDLC Flag sequence and is used to disable transmission of any bit oriented codes. When transmission is disabled the FEAC channel is set to all ones. Bit oriented codes are transmitted on the DS3 Far-End Alarm and Control channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the latest code has been transmitted at least 10 times. An interrupt or polling mechanism is used to determine when the most recent code written the XBOC register is being transmitted and a new code can be accepted. 9.19.2 DS3 Transmitter Timing Sources DS3 transmitter timing has three possible sources: 1. TICLK[3:1] input pins. If the system interface is SBI, then TEMUX-84 is the SBI bus clock master, and uses the SAJUST_REQ output signal to issue timing justification requests to the link-layer device. If the system interface is serial clock and data, TEMUX-84 derives TGAPCLK[3:1] from TICLK[3:1].) Integral DS3 clock synthesizer, which generates a gapped DS3 clock from the CLK52M input pin, in response to SBI bus timing justification requests from the link-layer device. TEMUX-84 is the SBI bus clock slave in this mode, and the SBI bus must be the system side option. External jitter attenuation is recommended when using this DS3 timing option. Recovered DS3 clock from the RCLK[3:1] input pins. If the system interface is SBI, then TEMUX-84 is the SBI bus clock master, as in case 1 above. If the system interface is serial clock and data, TEMUX-84 derives TGAPCLK[3:1] from the recovered DS3 clock.)
2.
3.
In each case, the DS3 transmitter drives the selected DS3 clock source onto the TCLK output pins of the DS3/E3 line side interface.
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9.20 DS3/E3 HDLC Transmitters The HDLC transmitter provides a serial data link for the DS3 C-bit parity path maintenance data link, E3 G.832 Network Operator byte, E3 G.832 General Purpose Communications Channel or E3 G.751 National Use bit. The HDLC transmitter is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRCCCITT frame check sequence (FCS) may be appended, followed by flags. If the HDLC transmitter data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the HDLC transmitter continuously transmits the flag sequence (01111110) until data is ready to be transmitted. The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The HDLC transmitter then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The HDLC transmitter will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO. A second mechanism transmits data when the FIFO depth has reached a user configured upper threshold. The HDLC transmitter will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences. Abort characters can be continuously transmitted at any time by setting the ABT bit. During packet transmission, an underrun situation can occur if data is not
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written before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt. 9.21 DS3/E3 Pseudo Random Pattern Generation and Detection (PRGD) The Pseudo Random Pattern Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer for the DS3/E3 payload. Patterns may be generated in the transmit direction, and detected in the receive direction. The patterns consume the entire payload; the overhead bits are ignored. Unframed patterns are not supported. Two types of ITU-T O.151 compliant test patterns are provided : pseudo-random and repetitive. The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7. The PRGD can be programmed to check for the generated pseudo random pattern. The PRGD can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. If a repetitive pattern is selected, the receiver will synchronize to any bit sequence that repeats with the programmed periodicity. A bit error accumulates when a bit disagrees with the original bit sequence synchronized to. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When a transfer is triggered, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next transfer. 9.22 M23 Multiplexer (MX23) The M23 Multiplexer (MX23) integrates circuitry required to asynchronously multiplex and demultiplex seven DS2 streams into, and out of, an M23 or C-bit Parity formatted DS3 serial stream. When multiplexing seven DS2 streams into an M23 formatted DS3 stream, the MX23 function performs rate adaptation to the DS3 by integral FIFO buffers. The C-bits are also generated and inserted. Software control is provided to transmit DS2 AIS and DS2 payload loopback requests. The loopback request is coded by inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7). The MX23 also
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supports generation of a C-bit Parity formatted DS3 stream by providing an internally generated DS2 rate clock corresponding to a 100% stuffing ratio. Integrated M13 applications are supported by providing an internally generated DS2 rate clock corresponding to a 39.1% stuffing ratio. When demultiplexing seven DS2 streams from an M23 formatted DS3, the MX23 performs bit destuffing via interpretation of the C-bits. The MX23 also detects and indicates DS2 payload loopback requests encoded in the C-bits. As per ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. DS2 payload loopback can be activated or deactivated under software control. During payload loopback the DS2 stream being looped back still continues unaffected in the demultiplex direction to the DS2 Framer. All seven demultiplexed DS2 streams can also be replaced with AIS on an individual basis under register control or they can be configured to be replaced automatically on detection of out of frame, loss of signal, RED alarm or alarm indication signal. 9.23 DS2 Framer (DS2 FRMR) The DS2 Framer (DS2-FRMR) integrates circuitry required for framing to a DS2 bit stream and is directly compatible with the M12 DS2 application. The DS2 FRMR frames to a DS2 signal with a maximum average reframe time of less than 7 ms. Both the F-bits and M-bits must be correct for a significant period of time before frame alignment is declared. Once in frame, the DS2 FRMR provides indications of the M-frame and M-subframe boundaries, and identifies the overhead bit positions in the incoming DS2 signal. Depending on configuration, declaration of DS2 out-of-frame occurs when 2 out of 4 or 2 out of 5 consecutive F-bits are in error (These two ratios are recommended in TR-TSY-000009 Section 4.1.2) or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled via the MBDIS bit in the DS2 Framer configuration register. Note that the DS2 framer is an off-line framer, indicating both OOF and COFA. Error events continue to be indicated even when the FRMR is indicating OOF, based on the previous frame alignment.
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The RED alarm and alarm indication signal are detected by the DS2 FRMR in 9.9 ms for DS2 format. The framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" DS2 M-frame intervals. For the RED alarm, a DS2 M-frame is said to be a "valid" interval if it contains a RED defect, defined as the occurrence of an OOF event during that M-frame. For AIS, a DS2 M-frame is said to be a "valid" interval if it contains AIS, defined as the occurrence of less than 9 zeros while the framer is out of frame during that Mframe. The discrepancy threshold ensures the detection algorithm operates in the presence of bit error rates of up to 10-3. Each "valid" DS2 M-frame causes an integration counter to increment; "non-valid" DS2 M-frame intervals cause a decrement. RED or AIS is declared if the associated integrator count saturates at 53, resulting in a detection time of 9.9 ms. RED or AIS declaration is deasserted when the associated count decrements to 0. The DS2 X-bit is extracted by the DS2 FRMR to provide an indication of far end receive failure. The FERF status is set to the current X/RAI state only if the two successive X/RAI bits were in the same state. The extracted FERF status is buffered for 6 DS2 M-frames before being reported within the DS2 FRMR Status register. This buffer ensures a virtually 100% probability of freezing the FERF status in a valid state during an out of frame occurrence. When an OOF occurs, the FERF value is held at the state contained in the last buffer location corresponding to the previous sixth M-frame. This location is not updated until the OOF condition is deasserted. Meanwhile, the last four of the remaining five buffer locations are loaded with the frozen FERF state while the first buffer location corresponding to the current M-frame is continually updated every Mframe based on the above FERF definition. Once correct frame alignment has been found and OOF is deasserted, the first buffer location will contain a valid FERF status and the remaining five buffer locations are enabled to be updated every M-frame. DS2 M-bit and F-bit framing errors are indicated. These error indications are accumulated for performance monitoring purposes in internal, microprocessor readable counters. The performance monitoring accumulators continue to count error indications even while the framer is indicating OOF. The DS2 FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS2 FRMR. 9.24 M12 Multiplexer (MX12) The M12 Multiplexer (MX12) integrates circuitry required to asynchronously multiplex and demultiplex four DS1 streams into, and out of, an M12 formatted
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DS2 serial stream as defined in ANSI T1.107 Section 7. The M12 multiplexer also supports the ITU-T Rec. G.747 standard for the multiplexing of three 2048 kbit/s streams into a 6312 kbit/s stream. When multiplexing four DS1 streams into an M12 formatted DS2 stream, the MX12 function performs logical inversion on the second and fourth tributary streams. Rate adaptation to the DS2 is performed by integral FIFO buffers, controlled by timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of sinusoidal jitter on the DS1 clocks for all jitter frequencies. X, F, M, and C bits are also generated and inserted by the timing circuitry. Software control is provided to transmit Far End Receive Failure (FERF) indications, DS2 AIS, and DS1 payload loopback requests. The loopback request is coded by inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7).Two diagnostic options are provided to invert the transmitted F or M bits. When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12 performs bit destuffing via interpretation of the C-bits. The MX12 also detects and indicates DS1 payload loopback requests encoded in the C-bits. As per ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. DS1 payload loopback can be activated or deactivated under software control. During payload loopback the DS1 stream being looped back still continues unaffected in the demultiplex direction. The second and fourth demultiplexed DS1 streams are logically inverted. All four demultiplexed DS1 streams can be replaced with AIS on an individual basis or can be configured for automatic replacement with AIS on detection of out of frame or RED alarm conditions. Similar functionality is supplied for supporting ITU-T Recommendation G.747. Software control is provided to transmit Remote Alarm Indication (RAI), 6312 kbit/s AIS, and the reserved bit. A diagnostic option is provided to invert the transmitted frame alignment signal and parity bit. When demultiplexing three 2048 kbit/s streams from a G.747 formatted 6312 kbit/s stream, bit destuffing is performed via interpretation of the C-bits. Tributary payload loopback can be activated or deactivated under software control. Although no remote loopback request has been defined for G.747, inversion of the one of the C-bits, as selected by the Loopback Code Select
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Register, triggers a loopback request detection indication in anticipation of Recommendation G.747 refinement. All three demultiplexed 2048 kbit/s streams can be replaced with AIS on an individual basis. 9.25 E3 Framer Three instances of the E3 Framer are independently programmed to frame to 34368 kbit/s frame formats. From each, the framed data is presented on RDATO[x] or mapped into the SBI bus. The E3-FRMR searches for frame alignment in the incoming serial stream based on either the G.751 or G.832 formats. For the G.751 format, the E3-FRMR expects to see the selected framing pattern error-free for three consecutive frames before declaring frame alignment. For the G.832 format, the E3-FRMR expects to see the selected framing pattern error-free for two consecutive frames before declaring frame alignment. Once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in G.832 format). While in-frame, the E3-FRMR also extracts various overhead bytes and processes them according to the framing format selected: In G.832 E3 format, the E3-FRMR extracts: * * the Trail Trace bytes; the FERF bit and indicates an alarm when the FERF bit is a logic 1 for 3 or 5 consecutive frames. The FERF indication is removed when the FERF bit is a logic 0 for 3 or 5 consecutive frames; the FEBE bit for accumulation in PMON; the Payload Type bits and buffers them so that they can be read by the microprocessor; the Timing Marker bit and asserts the Timing Marker indication when the value of the extracted bit has been in the same state for 3 or 5 consecutive frames; the Network Operator byte for processing by the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 1; the General Purpose Communication Channel byte for processing by the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 0.
* * * * *
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In G.751 E3 mode, the E3-FRMR extracts: * the Remote Alarm Indication bit (bit 11 of the frame) and indicates a Remote Alarm when the RAI bit is a logic 1 for 3 or 5 consecutive frames. Similarly, the Remote Alarm is removed when the RAI bit is logic 0 for 3 or 5 consecutive frames; the National Use reserved bit (bit 12 of the frame) for further processing in the HDLC receiver when the RNETOP bit in the E3 Data Link Control register is logic 0. Optionally, an interrupt can be generated when the National Use bit changes state. The E3-FRMR declares out of frame alignment if the framing pattern is in error for four consecutive frames. The E3-FRMR is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. Once the framer has determined the new frame alignment, the out-of-frame indication is removed and a COFA indication is declared if the new alignment differs from the previous alignment. The E3-FRMR detects the presence of AIS in the incoming data stream when less than 8 zeros in a frame are detected while the framer is OOF in G.832 mode, or when less than 5 zeros in a frame are detected while OOF in G.751 mode. This algorithm provides a probability of detecting AIS within a single frame in the presence of a 10-3 BER as 92.9% in G.832 and 98.0% in G.751. After five frames, the probability of detection rises to >99.999% for both formats. Loss of signal is LOS is declared when no marks have been received for 32 consecutive bit periods. Loss of signal is de-asserted after 32 bit periods during which there is no sequence of four consecutive zeros. E3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted. The E3-FRMR can also be enabled to automatically assert the RAI/FERF indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or AIS. The E3-FRMR can also be enabled to automatically insert G.832 FEBE upon detection of receive BIP-8 errors.
*
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9.26 E3 Transmitter Three E3 transmitters provide framing insertion for 34368 kbit/s unchannelized data from TDATI[3:1] or the SBI bus. The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible with the G.751 and G.832 framing formats. The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats. All overhead and status bits in each frame format can be individually controlled by register bits. While in certain framing format modes, the E3-TRAN generates various overhead bytes according to the following: In G.832 E3 format, the E3-TRAN: * * * * inserts the BIP-8 byte calculated over the preceding frame; inserts the Trail Trace bytes; inserts the FERF bit via a register bit or, optionally, when the E3-FRMR declares OOF, or when the loss of cell delineation (LCD) defect is declared; inserts the FEBE bit, which is set to logic 1 when one or more BIP-8 errors are detected by the receive framer. If there are no BIP-8 errors indicated by the E3-FRMR, the E3-TRAN sets the FEBE bit to logic 0; inserts the Payload Type bits based on the register value set by the microprocessor; inserts the Tributary Unit multiframe indicator bits either via the TOH overhead stream or by register bit values set by the microprocessor; inserts the Timing Marker bit via a register bit; inserts the Network Operator (NR) byte from the TDPR block when the TNETOP bit in the E3 Data Link Control register is logic 1; otherwise, the NR byte is set to all ones. All 8 bits of the Network Operator byte are available for use as a datalink;
* * * *
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*
inserts the General Purpose Communication Channel (GC) byte from the TDPR block when the TNETOP bit in the E3 Data Link Control register is logic 0; otherwise, the byte is set to all ones. In G.751 E3 mode, the E3-TRAN :
* *
inserts the Remote Alarm Indication bit (bit 11 of the frame) either via a register bit or, optionally, when the E3-FRMR declares OOF; inserts the National Use reserved bit (bit 12 of the frame) either as a fixed value through a register bit or from the HDLC transmitter as configured by the TNETOP bit in the E3 Data Link Control register and the NATUSE bit in the E3 TRAN Configuration register; optionally identifies the tributary justification bits and stuff opportunity bits as either overhead or payload for payload mappings that take advantage of the full bandwidth. Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes.
*
9.26.1 E3 Transmitter Timing Sources E3 transmitter timing has three possible sources: 1. TICLK[3:1] input pins. If the system interface is SBI, then TEMUX-84 is the SBI bus clock master, and uses the SAJUST_REQ output signal to issue timing justification requests to the link-layer device. If the system interface is serial clock and data, TEMUX-84 derives TGAPCLK[3:1] from TICLK[3:1].) Integral E3 clock synthesizer, which generates a gapped E3 clock from the CLK52M input pin, in response to SBI bus timing justification requests from the link-layer device. TEMUX-84 is the SBI bus clock slave in this mode, and the SBI bus must be the system side option. External jitter attenuation is recommended when using this E3 timing option. Recovered E3 clock from the RCLK[3:1] input pins. If the system interface is SBI, then TEMUX-84 is the SBI bus clock master, as in case 1 above. If the system interface is serial clock and data, TEMUX-84 derives TGAPCLK[3:1] from the recovered E3 clock.)
2.
3.
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In each case, the E3 transmitter drives the selected E3 clock source onto the TCLK output pins of the DS3/E3 line side interface. 9.27 E3 Trail Trace Buffer The Trail Trace Buffer (TTB) extracts and sources the trail trace message carried in the TR byte of the G.832 E3 stream. The message is used by the OS (operating system) to prevent delivery of traffic from the wrong source and is 16 bytes in length. The 16-byte message is framed by the PTI Multiframe Alignment Signal (TMFAS = 'b10000000 00000000). One bit of the TMFAS is placed in the most significant bit of each message byte. In the receive direction, the extracted message is stored in the internal RAM for review by an external microprocessor. By default, the byte of a 16-byte message with its most significant bit set high will be written to the first location in the RAM. The extracted trail trace message is checked for consistency between consecutive multiframes. A message received unchanged three or five times (programmable) is accepted for comparison with the copy previously written into the internal RAM by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched messages. In the transmit direction, the trail trace message is sourced from the internal RAM for insertion into the TR byte by the E3-TRAN. The Payload Type label carried in the MA byte of the G.832 E3 stream is also extracted. The label is used to ensure that the adaptation function at the trail termination sink is compatible with the adaptation function at the trail termination source. The Payload Type label is check for consistency between consecutive multiframes. A Payload Type label received unchanged for five frames is accepted for comparison with the copy previously written into the TTB by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched Payload Type label bits. 9.28 Tributary Payload Processor (VTPP) Each one of three tributary payload processors (VTPP) processes the virtual tributaries within an STS-1, AU3, or TUG3. The VTPP can be configured to process either VT1.5s or VT2s within an STS-1 or either TU11s or TU12s within an AU3 or TUG3. The number of tributaries managed by each VTPP ranges from 21 (when configured to process all VT2s or equivalently all TU12s) to 28 (when configured to process all VT1.5s or equivalently all TU11s). The Tributary payload processor is used in both the ingress and egress data paths. In the egress direction the pointer interpreter section of the VTPP can be bypassed on a per tributary basis to allow for pointer generator in the absence of
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valid pointers which is necessary when mapping floating transparent virtual tributaries from the SBI bus. 9.28.1 Incoming Multiframe Detector The multiframe alignment sequence in the path overhead H4 byte is monitored for the bit patterns of 00, 01, 10, 11 in the two least significant bits. If an unexpected value is detected, the primary multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift. The primary process will enter out of multiframe state (OOM). A new multiframe alignment is chosen, and OOM state is exited when four consecutive correct multiframe patterns are detected. Loss of multiframe (LOM) is declared after residing in the OOM state at the ninth H4 byte without re-alignment. In counting to nine, the out of sequence H4 byte that triggered the transition to the OOM state is counted as the first. A new multiframe alignment is chosen, and LOM state is exited when four consecutive correct multiframe patterns are detected. Changes in multiframe alignments are detected and reported. 9.28.2 Pointer Interpreter The pointer interpreter is a time-sliced state machine that can process up to 28 independent tributaries. The state vector is saved in RAM as directed by the incoming timing generator. The pointer interpreter processes the incoming tributary pointers such that all bytes within the tributary synchronous payload envelope can be identified and written into the unique payload first-in first-out buffer for the tributary in question. A marker that tags the V5 byte is passed through the payload buffer. The incoming timing generator directs the pointer interpreter to the correct payload buffer for the tributary being processed. The pointer interpreter processes the incoming pointers (V1/V2) as specified in the references. The pointer value is used to determine the location of the tributary path overhead byte (V5) in the incoming TUG3 or STS-1 (AU3) stream. 9.28.3 Payload Buffer The payload buffer is a bank of FIFO buffers. It is synchronous in operation and is based on a time-sliced RAM. The three 19.44 MHz clock cycles in each 6.48 MHz period are shared between the read and write operations. The pointer interpreter writes tributary payload data and the V5 tag into the payload buffer. A 16 byte FIFO buffer is provided for each of the (up to 28) tributaries. Address information is also passed through the payload buffer to allow FIFO fill status to be determined by the pointer generator.
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9.28.4 Pointer Generator 1. The pointer generator block generates the tributary pointers (V1/V2) as specified in the references. The pointer value is used to determine the location of the tributary path overhead byte (V5) on the outgoing stream. The pointer generator is a time-sliced state machine that can process up to 28 independent tributaries. The state vector is saved in RAM at the address associated with the current tributary. The pointer generator fills the outgoing tributary synchronous payload envelopes with bytes read from the associated FIFO in the payload buffer for the current tributary. The pointer generator creates pointers in the V1-V3 bytes of the outgoing data stream. The marker that tags the V5 byte that is passed through the payload buffer is used to align the pointer. The outgoing timing generator directs the pointer generator to the FIFO in the payload buffer that is associated with the tributary being processed. The pointer generator monitors the fill levels of the payload buffers and inserts outgoing pointer justifications as necessary to avoid FIFO spillage. Normally, the pointer generator has a FIFO dead band of two bytes. The dead band can be collapse to one so that any incoming pointer justifications will be reflected by a corresponding outgoing justification with no attenuation. Signals are output by the pointer generator that identify outgoing V5 bytes and the tributary synchronous payload envelopes. On a per tributary basis, tributary path AIS and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. The idle code is selectable globally for the entire VC3 or TUG3 to be all-zeros or all-ones. It is also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. Tributary path AIS is automatically inserted into outgoing tributaries if the pointer interpreter detects tributary path AIS on the corresponding incoming tributary. 9.29 Receive Tributary Path Overhead Processor (RTOP) Each one of three tributary path overhead processors (RTOP) monitors the outgoing stream of the tributary payload processor (VTPP) and processes the tributaries within an STS-1, AU3, or TUG3. The RTOP can be configured to process all the VT1.5s or VT2s that can be carried in an STS-1 or all the TU11s or TU12s that can be carried in an AU3 or TUG3. The number of tributaries managed by each RTOP ranges from 21 (when configured to process all VT2s or all TU12s) to 28 (when configured to process all VT1.5s or all TU11s). The RTOP provides tributary performance monitoring of incoming tributaries. Bit interleaved parity of the incoming tributaries is computed and compared with the BIP-2 code encoded in the V5 byte of the tributary. Errors between the computed
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and received values are accumulated. RTOP also accumulates far end block error codes. Incoming path signal label is debounced and compared with the provisioned value. Path signal label unstable, path signal label mismatch and change of path signal label event are identified. 9.29.1 Error Monitor The error monitor block contains a set of 12-bit counters that are used to accumulate tributary path BIP-2 errors, and a set of 11-bit counters to accumulate far end block errors (FEBE). The contents of the counters may be transferred to a holding RAM, and the counters reset under microprocessor control. Tributary path BIP-2 errors are detected by comparing the tributary path BIP-2 bits in the V5 byte extracted from the current multiframe, to the BIP-2 value computed for the previous multiframe. BIP-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. Far end block errors (FEBEs) are detected by extracting the FEBE bit from the tributary path overhead byte (V5). Tributary path remote defect indication (RDI) and remote failure indication (RFI) are detected by extracting bit 8 and bit 4 respectively of the tributary path overhead byte (V5). The RDI is recognized when bit 8 of the V5 byte is set high for five or ten consecutive multiframes while RFI is recognized when bit 4 of V5 is set high for five or ten consecutive frames. The RDI and RFI bits may be treated as a two-bit code word. A code change is only recognized when the code is unchanged for five or ten frames. The tributary path signal label (PSL) found in the tributary path overhead byte (V5) is processed. An incoming PSL is accepted when it is received unchanged for five consecutive multiframes. The accepted PSL is compared with the associated provisioned value. The PSL match/mismatch state is determined by the following:
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Table 2 Path Signal Label Mismatch State Expected PSL 000 000 000 001 001 001 XXX 000, 001 XXX 000, 001 XXX 000, 001 XX 000, 001 Accepted PSL 000 001 XXX 000 000 001 XXX 001 000 001 XXX YYY PSLM State Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch
Each time an incoming PSL differs from the one in the previous multiframe, the PSL unstable counter is incremented. Thus, a single bit error in the PSL in a sequence of constant PSL values will cause the counter to increment twice, once on the errored PSL and again on the first error-free PSL. The incoming PSL is considered unstable when the counter reaches five. The counter is cleared when the same PSL is received for five consecutive multiframes. 9.30 Receive Tributary Trace Buffer (RTTB) When configured for SONET compatible operation, each one of three receive tributary trace buffers (RTTB) processes the tributary trace message of all the tributaries in an STS-1 stream. Each of the seven tributary groups (VT groups) may be independently configured to accept any of the four tributary types (VT1.5, VT2, VT3, and VT6). The RTTB extracts tributary trace message from each tributary and stores it in one of a set of internal buffers. The RTTB may be configured for SDH compatible operation. The incoming stream may carry an AU3 of an STM1 stream or a TUG3 in an AU4 of an STM1 stream.
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The tributary trace message of each tributary is extracted form the J2 (J1 in TU3 mode) byte. It is written to the internal buffer corresponding to the tributary. The internal buffer may behave as a simple circular buffer, or optionally, be synchronized to the framing pattern embedded in the message. For a 16-byte trail trace identifier, the first byte is identified by a logic one in the most significant bit. For a 64-byte tributary trace message, the last two bytes are set to the ASCII characters for carriage-return (CR) and linefeed (LF). An extracted message is declared the accepted message, if it is received unchanged for 3 multiframes. The accepted message is compared with the locally provisioned expected message. A tributary trace identifier mismatch alarm (TIM) is asserted when the accepted and expected messages differ. Conversely, TIM is negated when the messages are identical. An interrupt is optionally generated upon a change in the TIM state. Messages of all-zeros bytes cannot become accepted and, therefore, have no effect on the TIM state. The RTTB also monitors for tributary trace unstable conditions. Each time a tributary trace message that is received differs from the previous message, the unstable counter is incremented by one. The tributary trace unstable alarm (TIU) is asserted when the unstable counter reaches eight. The unstable counter is cleared and the unstable alarm negated when the extracted message remains unchanged for enough multiframes to meet the acceptance criteria. An interrupt is optionally generated upon a change in the TIU state. 9.31 Receive Tributary Bit Asynchronous Demapper (RTDM) Each one of three Receive Tributary Demappers (RTDM) demaps up to 28 T1 or 21 E1 bit asynchronous mapped signals from an STS-1 SPE, TUG3 within a STM-1/VC4 or STM-1 VC3 payload.
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Table 3 Asynchronous T1 Tributary mapping
V5 RRRRRRIR 24 bytes - 8I J2 C1C2OOOOIR 24 bytes - 8I Z6 C1C2OOOOIR 24 bytes - 8I Z7 C1C2RRRS1S2R 24 bytes - 8I
R: Fixed Stuff bit - set to logic `0' or `1' C: Stuff Control bit - set to logic `1' for stuff indication S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit O: Overhead I: T1 payload information
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Table 4 Asynchronous E1 Tributary Mapping
V5 R 32 bytes - 8I R J2 C1C2OOOORR 32 bytes - 8I R Z6 C1C2OOOORR 32 bytes - 8I R Z7 C1C2RRRRRS1 S2I I I I I I I 31 bytes - 8I R
R: Fixed Stuff bit - set to logic `0' or `1' C: Stuff Control bit - set to logic `1' for stuff indication S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit O: Overhead I: E1 payload information The RTDM buffers the tributary synchronous payload envelope bytes of the incoming tributaries in individual FIFOs to accommodate tributary pointer justifications. The RTDM performs majority voting on the tributary stuff control (C1, C2) bits. If the majority of each set of the stuff control bits indicate a stuff operation, then the associated stuff opportunity bit (S1, S2) will not carry T1 or E1 payload.
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Conversely, if the majority of the stuff control bits indicate a data operation, the appropriate stuff opportunity bit(s) will carry T1 or E1 payload. The RTDM, in cooperation with the T1/E1 jitter attenuator, attenuates jitter introduced by pointer justification events. The T1/E1 jitter attenuator may be bypassed, in which case an external device may use the SBI Link Rate Octet generated by RTDM to determine the clock phase. When a pointer justification is detected, the RTDM issues evenly spaced 1/12 UI T1 adjustments or 1/9 UI E1 adjustments encoded in the SBI Link Rate Octet. The RTDM optionally acts as a time switch. When time switching is enabled, the association of timeslots on the system interface (SBI or H-MVIP) to incoming tributaries is software configurable. There are two pages in the time switch configuration RAM. One page is software selectable to be the active page and the other the stand-by page. The configuration in the active page is used to switch incoming tributaries. The stand-by page can be programmed to the next switch configuration. Change of page selection is effected immediately. The one constraint on switch configuration is that the all the remapped tributaries in an SPE must be of the same type (T1 or E1). 9.32 Receive Tributary Byte Synchronous Demapper Each one of three Receive Tributary Byte Synchronous Demappers demaps up to 28 T1 or 21 E1 byte synchronous mapped signals from an STS-1 SPE, TUG3 within a STM-1/VC4 or STM-1 VC3 payload. The demapping is done inaccordance with ITU-T Recommendation G.709 and ANSI T1.105. Byte synchronous demapping is enabled on a per-tributary basis by setting the ENBL bit through the Byte Synchronous Demapping Tributary Control RAM Indirect Access Data register and by bypassing the receive jitter attenuator by setting the RJATBYP bit through the RJAT Indirect Channel Data register. Given that frame alignment is provided by the mapping function, the T1/E1 framer doesn't provide the frame alignment for the system interface. If the tributary `F' bit position contains valid framing information, the T1/E1 framer may be used for performance and alarm monitoring. Signaling, if present, may be dealt with in two ways for T1. By default, the T1 framer attempts to find frame and extracts the signaling from the robbed bit signaling positions. Alternately, the values encoded in the S1S2S3S4 bit positions are presented on the system interface verbatim without debounce or freezing if the RAWSIG bit programmed through the SIGX Indirect Channel Data
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registers is logic 1. This is programmed on a per-tributary basis. For E1, the signaling is extracted from "Multiframe alignment signal" byte. 9.33 DS3 Mapper Drop Side (D3MD) Each one of three DS3 Mapper DROP Side (D3MD) blocks demaps a DS3 signal from an STS-1 (STM-0/AU3) payload. The demapped DS3 is presented to the DS3 framer and subsequently presented on RDAT[x]. Optionally, it is mapped into the SBI bus or demultiplexed into 28 DS1s or 21 E1s. The asynchronous DS3 mapping consists of 9 rows every 125 s (8 KHz). Each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. Fixed stuff bytes are used to fill the remaining bytes. The asynchronous DS3 mapping is shown in Table 5. Table 5 Asynchronous DS3 mapping to STS-1 (STM-0/AU3)
J1 2 x 8R 2 x 8R 2 x 8R STS POH 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII RRCIIIII 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 25 x 8I 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R 2 x 8R CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS CCRROORS 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I 26 x 8I
R: Fixed Stuff bit - set to logic `0' or `1' C: Stuff Control bit - set to logic `1' for stuff indication S: Stuff Opportunity bit - when stuff control bit is `0', stuff opportunity is I bit O: Overhead communication channel I: DS3 payload information 9.33.1 DS3 Demapper The D3MD performs majority vote on the received C-bits. If 3 out of 5 C-bits are `1's, the associated S bit is interpreted as a stuff bit. If 3 out of 5 C-bits are `0's,
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the associated S bit is interpreted as an Information bit. The information bits are written to an elastic store and the Fixed Stuff bits (R) are ignored. Given a path signal label mismatch (PSLM) or path signal label unstable (PSLU), the D3MD ignores the STS-1 (STM-0/AU3) SPE and writes a DS3 AIS pattern to the elastic store. In addition, the desynchronization algorithm assumes a nominal ratio of data to stuff bits carried in the S bits (1 out of 3 S bits is assumed to be an information (data) bit). DS3 AIS is shown in Table 6. Table 6 DS3 AIS format
X (1) X (1) P (p) P (p) M (0) M (1) M (0) D F (1) D C (0) D F (0) D C (0) D F (0) D C (0) D F (1) D D D D D D D F (1) F (1) F (1) F (1) F (1) F (1) D D D D D D C (0) C (0) C (0) C (0) C (0) C (0) D D D D D D F (0) F (0) F (0) F (0) F (0) F (0) D D D D D D C (0) C (0) C (0) C (0) C (0) C (0) D D D D D D F (0) F (0) F (0) F (0) F (0) F (0) D D D D D D C (0) C (0) C (0) C (0) C (0) C (0) D D D D D D F (1) F (1) F (1) F (1) F (1) F (1) D D D D D D
*
valid M-frame alignment bits (M-bits), M-subframe alignment bits (F-bits), and parity bit of the preceding M-frame (P-bits). The two P-bits are identical, either both are zeros or ones. all the C-bits in the M-frame are set to zeros the X-bits are set to ones the information bit (84 Data bits with repeating sequence of 1010..)
* * *
9.33.2 DS3 Demapper Elastic Store The elastic store block is provided to compensate for frequency differences between the DS-3 stream extracted from the STS-1 (STM-0/AU3) SPE and the CLK52M clock input. The DS3 Demapper extracts I bits from the STS-1 (STM-0/AU3) SPE and writes the bits into a 128 bit (16 byte) elastic store. Eight bytes are provided for SONET/SDH overhead (3 bytes for TOH, 1 byte for a positive stuff, 1 byte for POH) and DS3 reserve stuffing bits (2 bytes for R bits, and 3 overhead bits which is rounded-up to 1 byte). The remaining 8 bytes are provided for path pointer adjustments.
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Data is read out of the Elastic Store using a divide by 8 version of the input CLK52M clock. If an overflow or underflow condition occurs, an interrupt is optionally asserted and the Elastic Store read and write address are reset to the startup values (logically 180 degrees apart). 9.33.3 DS3 Desynchronizer The Desynchronizer monitors the Elastic Store level to control the de-stuffing algorithm to avoid overflow and underflow conditions. The Desynchronizer assumes either a 51.84 MHz clock or a 44.928 MHz clock (provided via input CLK52M). When using a 44.928 MHz CLK52M clock, the DS3 clock is generated using a fixed 8 KHz interval. The 8KHz interval is subdivided into 9 rows. Each row contains either 621 or 622 clock periods. The CLK52M contains 624 cycles per row. To generate 621 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 207 clocks + 1 clock gap is used. To generate 622 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 208 clocks is used. When using a 51.84 MHz CLK52M clock, the DS3 clock is generated using similar gapping patterns. To generate 621 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 36 * (5 clocks + 1 clock gap) is used. To generate 622 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 35 * (5 clocks + 1 clock gap) + 6 clocks) is used. Table 7 illustrates the gap patterns used to generate the desynchronized DS3 clock under the normal, DS3 AIS, faster and slower status. The faster pattern is used to drain the elastic store to avoid overflows. The slower pattern is used to allow the elastic store to fill to avoid underflows.
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Table 7 DS3 desynchronizer clock gapping algorithm Row Number 1 2 3 4 5 6 7 8 9 Normal or DS3 AIS 621 621 622 621 621 622 621 621 622 Run Faster 621 621 622 621 622 622 621 622 622 Run Slower 621 621 622 621 621 621 621 621 621
9.34 Transmit Tributary Path Overhead Processor (TTOP) Each one of three Transmit Tributary Path Overhead Processors (TTOP) generates the path overhead for up to 28 VT1.5/TU-11s or 21 VT2/TU-12s. When configured for SONET compatible operation, the TTOP inserts the four tributary path overhead bytes (V5, J2, Z6, and Z7) to each tributary. The TTOP may also be configured for SDH compatible operation. The incoming STM-1 stream may carry three AU3s or an AU4 with three TUG3s. The TTOP computes the BIP-2 code in the current tributary SPE and inserts the result into the BIP-2 bits of the V5 byte in the next tributary SPE. The tributary path signal label in the V5 byte of each tributary can be sourced from internal registers. The tributary far end block error bit in the V5 byte of each tributary is inserted based of the BIP error count detected at a companion RTOP block. The tributary remote failure indication and remote defect indication bits in the V5 or the Z7 byte of each tributary is inserted based on the tributary alarm status of the companion RTOP TSB. The TTOP inserts the tributary trail trace identifier (TTI) into the J2 byte. Each tributary is provided with a 64-byte buffer to store the identifier. To transmit a 16byte message, one must write four identical copies to the buffer. One shadow buffer is available for temporary replacement of a selected transmitted TTI while the 64-byte identifier buffer is being updated. Data is retrieved sequentially from the active buffer at each J2 byte position. No CRC insertion is performed; any CRC must be written into the trail trace buffer. The shadow buffer can be
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programmed with new messages without timing constraints when inactive. An inactive 64-byte identifier buffer can also be programmed with new messages without timing constraints. Programming for TTI buffers is done one buffer at a time by first programming the shadow buffer, switching to the shadow buffer for the desired tributary, updating the desired tributary identifier buffer and finally switching back from the shadow buffer to the tributary buffer. Switching between the shadow buffer and normal buffer is synchronized to the start of each identifier on a per-tributary basis. 9.35 Transmit Remote Alarm Processor (TRAP) When configured for SONET compatible operation, each one of three TRAP SONET/SDH Transmit Remote Alarm Processors processes remote alarm indications of tributaries in an STS-3 stream. The virtual tributaries within an STS-1 stream may be configured to accept either VT1.5 or VT2 tributary types. The TRAP may also be configured for SDH compatible operation. The incoming STM-1 stream may carry three AU3s or an AU4 with three TUG3s. Two methods of encoding tributary remote alarms are supported, as selected on a per-tributary basis by the ERDI bits of the TRAP Control registers and TTOP Control registers. If the ERDI bits for a tributary are logic 0, RDI-V is transmitted by setting bit 8 of the V5 byte to logic 1 and RFI-V is transmitted by setting bit 4 of the V5 byte to logic 1. Bits 6 and 7 of the Z7 will be zeros. If the ERDI bits for a tributary are logic 1, extended RDI is effected. The triggers for ERDI-V are programmable, but the following is always true if ERDI is configured: bit 8 of the V5 byte equals bit 5 of the Z7 byte, bit 7 of the Z7 byte is always the complement of bit 6 of the Z7 byte, and if byte synchronous mapping is being used, bit 4 of V5 will equal the value programmed through the Byte Synchronous Mapping Tributary Control Indirect Access Data register; otherwise, it will be logic 0.
If the FORCEEN bit of the TRAP Control register is logic 1 then bit 8 of V5 (plus bit 5 of Z7 if ERDI) reflects the state of the RDI bit of the TRAP Control register and the ARDI bit of the TRAP Control register sets bit 6 of Z7 if ERDI; otherwise it sets bit 4 of V5. If FORCEEN is logic 0, the source for RDI-V and RFI-V can be any one of the RADEAST input, the RADWEST input or Telecom Drop bus alarms. The TRAP may be configured to insert tributary remote defect indications (RDI-V), tributary remote fault indications (RFI-V) and tributary remote error indications (REI-V) based on alarms detected in tributaries received on the
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Telecom Drop bus, LDDATA[7:0]. The contents of the SONET/SDH Master Tributary Remote Defect Indication Control register determine which alarms affect the state of bit 8 of V5 and (if ERDI is set) bit 5 of Z7. The contents of the SONET/SDH Master Tributary Auxiliary Remote Defect Indication Control register determine the which alarms affect the state of bit 4 of V5 if not ERDI or bit 6 of Z7 if ERDI. Alternatively, the TRAP may also be configured to extract RDI-V, RFI-V and REIV from two independent serial remote alarm ports, RADEAST and RADWEST. In all cases, the RDI-V and RFI-V state will be sent for a minimum of 10 multiframes before changing, unless a higher priority alarm is required. The TRAP provides selection between the Telecom Drop bus alarms and the two remote serial alarm ports for the source of remote alarm status on a per-tributary basis. By default, all three sources are disabled. Tributaries in any of the three sources of remote alarms can be mapped to arbitrary tributaries in the outgoing data stream. The mapping is configured through the TRAP Indirect Remote Alarm Page Address, TRAP Indirect Remote Alarm Tributary Address and TRAP Indirect Datapath Tributary Data registers. A valid TU designation written via the TRAP Indirect Datapath Tributary Data register is all that is required to enable the alarms for the outgoing tributary specified by the TRAP Indirect Remote Alarm Tributary Address register. Although it is possible to have any subset of the three sources enabled, it is usual to have only one of the three sources enabled for a particular tributary. 9.36 Transmit Tributary Bit Asynchronous Mapper (TTMP) Each one of three Transmit Tributary Mapper blocks bit asynchronously maps up to 28 T1 or 21 E1 streams into an STS-1 SPE, TUG3 in a STM-1/VC4 or STM1/VC3 payload. The TTMP compensates for any frequency differences between the incoming individual serial bit rates and the available STS-1 or STM-1/VC3 payload capacity. The asynchronous T1 mapping consists of 104 octets every 500 s (2 KHz). The asynchronous E1 mapping consists of 140 octets every 500 s (2 KHz). Refer to the RTDM block for a description of the asynchronous T1 and E1 mappings. The tributary mapper is a time-sliced state machine which uses a payload buffer as an elastic store. The T1 or E1 streams are read from the payload buffer, and mapped into VT1.5 Payloads and VT2 Payloads using bit asynchronous mapping only. The Tributary Mapper compensates for phase and frequency offsets using bit stuffing. A jitter-reducing control loop is used to monitor the Payload Buffer depth
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and reduce mapping jitter to 1.0 UI. To reduce mapping jitter even further, a dither technique is inserted between the control loop and the stuff bit generator resulting in an acceptable desynchronizer mapping jitter of about 0.3 UI. The Tributary Mapper may optionally act as a time switch. When Time Switch Enable is active, the association of Tributary Mapper VT Payloads to logical FIFO data streams is software configurable. There are two pages in the time switch configuration RAM. One page is software selectable to be the active page and the other the stand-by page. The configuration in the active page is used to associate outgoing VT Payloads to logical FIFOs. The stand-by page can be programmed to the next switch configuration. Change of page selection is synchronized to incoming stream frame boundaries. When Time Switch Enable is inactive, the association of outgoing VT Payloads to logical FIFOs is fixed. The TTMP outputs the STS-1, TUG3 in a STM-1/VC4 or STM-1/VC3 with the bit asynchronous mapped T1s or E1s onto an internal bus for further processing by the Transmit Tributary Payload Processor block. 9.37 Transmit Tributary Byte Synchronous Mapper Each one of three Transmit Tributary Mapper blocks byte synchronously maps up to 28 T1 or 21 E1 streams into an STS-1 SPE, TUG3 in a STM-1/VC4 or STM1/VC3 payload. The mapping is done inaccordance with ITU-T Recommendation G.709 and ANSI T1.105. Byte synchronous mapping is enabled on a per-tributary basis by setting the ENBL bit through the Byte Synchronous Mapping Tributary Control RAM Indirect Access Data register, by bypassing the transmit jitter attenuator by setting the TJATBYP bit through theTJAT Indirect Channel Data register and by disabling the egress VTPP pointer interpretation via the EPTRBYP or ETVTPTRDIS bits. By default the T1/E1 framer inserts valid framing into the T1 `F' bit and E1 TS0. The T1 signaling received from the system interface is encoded into the S1S2S3S4 bit positions. Signaling is also inserted into the robbed bit signaling positions as enabled by the SIGC bits programmed through the TPCC Indirect Channel Data registers. For E1, the signaling insertion is independent of the mapping. 9.37.1 Jitter The byte synchronous mapping protocol does not provide the capability to perform individual bit stuffs; rate adaptation is achieved through VT pointer
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justifications. A pointer justification introduces 8 UI of jitter. No special techniques are employed to shape the frequency spectrum of this jitter. To avoid introducing jitter, it is recommended that one avoid VT pointer justifications. If transmit timing is derived from the SBI Add bus data rate, SBI bus pointer movements should be avoided. If transmit timing is locked to CTCLK, then CTCLK should be locked to SREFCLK. 9.38 DS3 Mapper ADD Side (D3MA) Each one of three DS3 Mapper ADD Side (D3MA) blocks maps a DS3 signal into an STS-1 (STM-0/AU3) payload and compensate for any frequency differences between the incoming DS3 serial bit rate (TICLK) and the available STS-1 (STM-0/AU3) SPE mapped payload capacity. The asynchronous DS3 mapping consists of 9 rows every 125 s (8 KHz). Each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. Fixed stuff bytes are used to fill the remaining bytes. Please refer to section 9.33 for a description of the DS3 mapping. 9.38.1 DS3 Mapper Serializer High speed serial data from the DS3-TRAN block is deserialized and written into the Elastic Store. 9.38.2 DS3 Mapper Elastic Store The elastic store block is provided to compensate for frequency differences between the DS3 stream from the DS3-TRAN block and the STS-1 (STM-0/AU3) SPE capacity. The DS3 Serializer writes data into the elastic store at the TICLK/8 rate while data is read out at the stuffed STS-1 (STM-0/AU3) byte rate. If an overflow or underflow condition occurs, an interrupt is optionally asserted and the Elastic Store read and write address are reset to the startup values (logically 180 degrees apart). The Elastic store is 128 bits (16 bytes) to allow for a fixed read/write pointer lag of 7 bytes (3 bytes for TOH, 1 byte for POH, 2 bytes for R bits, and 3 overhead bits which is rounded-up to 1 byte). Four bytes are also added on either side for positive and negative threshold detection. 9.38.3 DS3 Synchronizer The DS3 Synchronizer performs the mapping of the DS3 into the STS-1 (STM-0/AU3) SPE. The DS3 Synchronizer monitors the Elastic Store level to
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control the stuffing algorithm to avoid overflow (i.e. run faster) and underflow (i.e. run slower) conditions. The fill level of the elastic store is monitored and stuff opportunities in the DS3 mapping are used to center the Elastic Store. To consume a stuff opportunity, the five C-bits on a row are set to ones and the S bit is used to carry an DS3 information bit. When the S bit is not used to carry information, the C-bits on the row are set to zeros. The DS3 synchronizer uses a fixed bit leaking algorithm which leaks 8 bits of phase buildup in 500 s. The 8 kHz STS-1 (STM-0/AU3) frame interval is subdivided into 9 rows. Each row contains one stuff opportunity. Table 8 illustrates the stuffing implementation where S means stuff bit and I means an information bit (DS3 data). Table 8 DS3 synchronizer bit stuffing algorithm Row Number 1 2 3 4 5 6 7 8 9 Normal or DS3 AIS S S I S S I S S I Run Faster S S I S I I S I I Run Slower S S I S S S S S S
Under microprocessor control, the incoming DS3 stream can be overwritten with the framed DS3 AIS. When asserting DS3 AIS, a nominal stuff pattern is used as illustrated above. Please refer to the D3MD functional description section for a description of the DS3 AIS frame. The D3MA outputs the STS-1 (STM-0/AU3) with the mapped DS3 onto the Line Add bus, LADATA[7:0]. 9.39 Egress H-MVIP System Interface The Egress H-MVIP System Interface (Figure 14) provides system side H-MVIP access for up to 84 T1 or 63 E1 transmit streams. There are three separate interfaces for data, CAS signaling and CCS signaling. The H-MVIP signaling
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interfaces can be used in combination with the SBI interface in certain applications. Control of the system side interface is global to TEMUX-84 and is selected through the SYSOPT[1:0] bits in the Global Configuration register. The system interface options are H-MVIP, SBI bus and SBI bus with CAS or CCS HMVIP. Figure 14 Egress Clock Slave: H-MVIP
TRANSMITTER
CTCLK MVED[1:21] CASED [1:21] C CSED [1:3] C MVFP B CMVFPC C MV8MCLK Egress System Inte rface EL ST Elastic Store T1/E1Transmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Co nditioning
TJAT Digital PLL TJAT FIFO
to DS3 Multiplexer or SONET/SDH Mapper
Inputs Tim ed to CMV8MCLK
When Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP egress interface multiplexes up to 2016 channels from 84 T1s or 63 E1s, up to 2016 channel associated signaling (CAS) channels from 84 T1s or 63 E1s and common channel signaling from up to 84 T1s or 63 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. Twenty-one H-MVIP data signals, MVED[1:21], share pins with the SBI inputs to provide H-MVIP access for up to 2016 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192 Mbit/s H-MVIP signal. This mode is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to H-MVIP. The option exists to transmit at a rate locked to the CTCLK input, to a selected recovered clock or to be looped timed. Regardless of transmit timing source, the transmit elastic store must not be bypassed. A separate twenty-one signal H-MVIP interface is for access to the channel associated signaling for 2016 channels. The CAS H-MVIP interface is time division multiplexed exactly the same way as the data channels. The CAS HMVIP is synchronized with the H-MVIP data channels when SYSOPT[1:0] is set to H-MVIP mode. Over a T1 or E1 multi-frame, the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte. Optionally, the third and fourth bit of each byte may be used as inband control of whether CAS signalling is inserted or whether the timeslot is 64 kbit/s clear channel.
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The CAS H-MVIP interface can be used in parallel with the SBI Add bus as an alternative method for accessing the CAS bits while data transfer occurs over the SBI bus. This is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface". A separate H-MVIP interface consisting of three signals is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSED[1:3], is not multiplexed with any other pins. CCSED[1:3] can be used in parallel with the Clock Slave:H-MVIP mode when SYSOPT[1:0] is set to "H-MVIP Interface" or in parallel with the SBI Add bus when SYSOPT[1:0] is set to "SBI Interface with CAS or CCS H-MVIP Interface". The TS16 CCS and V5 channels for E1 tributaries and channel 24 CCS for T1 tributaries can be enabled when the CCS16EN, CCS15EN, CCS31EN and/or CCSEN context bits are set to logic 1 through the T1/E1 Transmitter Indirect Channel Data Registers. When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a transmit signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. 9.40 Ingress System H-MVIP Interface The Ingress System Interface (Figure 15) provides H-MVIP access for up to 84 T1 or 63 E1 receive streams. When enabled for 8.192 Mbit/s H-MVIP there are three separate interfaces for data and signaling. The H-MVIP signaling interfaces can be used in combination with the SBI interface in certain applications. Control of the system side interface is global to TEMUX-84 and is selected through the SYSOPT[1:0] bits in the Global Configuration register at address 0x0002. The system interface options are H-MVIP, SBI bus and SBI bus with CAS or CCS HMVIP. The ingress H-MVIP interface is always a clock slave. Figure 15 Ingress Clock Slave: H-MVIP
RECEIVER
MVID [1:21] CASID[1:21] CC SID[1 :3] C MVFP CMVFPC C MV8MCLK
Inputs Tim ed to CM V8M CLK
ELST Elastic Store Ingress System Interface
T1/E1 FRM R Framer: Frame A lignment, Alarm Extraction
R JAT D igital Jitter Attenuator
From D S3 Multiplexer or SONET/SD H mapper
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When Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP ingress interface multiplexes up to 2016 channels from 84 T1s or 63 E1s, up to 2016 channel associated signaling (CAS) channels from 84 T1s or 63 E1s and common channel signaling (CCS) from up to 84 T1s or 63 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. The three ingress H-MVIP interfaces operate independently except that using any one of these forces the T1 or E1 framer to operate in synchronous mode, meaning that elastic stores are used. Twenty-one H-MVIP data signals, MVID[1:21] provide H-MVIP access for up to 2016 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192 Mbit/s H-MVIP signal. This mode is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to H-MVIP. A separate H-MVIP interface consisting of twenty-one pins is for access to the channel associated signaling for all of the 2016 data channels. The CAS is time division multiplexed exactly the same way as the data channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame, the four CAS bits per channel are repeated with each data byte. The CAS H-MVIP interface can be used in parallel with the SBI Drop bus as an alternative method for accessing the CAS bits while data transfer occurs over the SBI bus. This is selected when the SYSOPT[1:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface". A separate H-MVIP interface consisting of three signals is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSID[1:3], is not multiplexed with any other pins. The CCSID[1:3] outputs is always available provided CMV8MCLK, CMVFPB and CMVFPC are active.The TS0ID output provides the contents of E1 TS0. When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a receive signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. 9.41 Extract Scaleable Bandwidth Interconnect (EXSBI) The Extract Scaleable Bandwidth Interconnect block demaps up to 84 1.544 Mbit/s links, 63 2.048 Mbit/s links, three 44.736 Mbit/s links, three
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34.386 Mbit/s links or an arbitary bit rate from the SBI shared bus. The SBI bandwidth is evenly divided into three SPEs, each of which may carry a different payload type. The 1.544 Mbit/s links can be unframed or they can be T1 framed and channelized for insertion into the DS3 multiplex or SONET/SDH mapping. The 2.048 Mbit/s links can be unframed or they can be E1 framed and channelized for insertion into the SONET/SDH mapping or G.747 multiplexer. The 44.736 Mbit/s links can also be unframed for mapping into SONET/SDH. The 44.736 Mbit/s links and 34.368 Mbit/s links can be DS3/E3 unchannelized when the TEMUX-84 is used as a DS3/E3 framer. Finally, an arbitrary bandwidth signal may be carried for presentation on the Flexible Bandwidth Port. The SBI Bus Data Formats section provides the details of the mapping formats. All egress links extracted from the SBI bus can be timed from the source or from the TEMUX-84. When timing is from the source, the 1.544 Mbit/s, 2.048 Mbit/s, 34.368 Mbit/s or 44.736 Mbit/s internal clocks are slaved to the arrival rate of the data. For 34.368 Mbit/s or 44.736 Mbit/s data streams there is also the option of using timing link rate adjustments provided from the source and carried with the links over the SBI bus. A T1/E1 tributary may be transmitted at a rate different from that of the SBI bus if the tributary is looped timed, locked to the CTCLK input or locked to a selected recovered clock. In this case, the frame slip buffer (ELST) must be used to adapt the data rate. The 44.736 Mbit/s or 34.368 Mbit/s clock is synthesized from the 51.84 MHz or 44.928 MHz reference clock, CLK52M. Using either reference clock frequency, the 44.736 Mbit/s or 34.368 Mbit/s rate is generated by gapping the reference clock in a fixed way. Timing adjustments are performed by adding or deleting four clocks over the 500 mS period. When the TEMUX-84 is the SBI egress clock master for a link, clocks are sourced from within the TEMUX-84. The data rate is set by the frequency of the CTCLK input, one of the three recovered clocks (RECVCLK1, RECVCLK2, or RECVCLK3) or the tributary receive clock if loop timed. Based on buffer fill levels, the EXSBI sends link rate adjustment commands to the link source indicating that it should send one additional or one fewer bytes of data during the next 500 mS interval. Failure of the source to respond to these commands will ultimately result in overflows or underflows which can be configured to generate per link interrupts. Channelized T1s extracted from the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s.
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9.42 Insert Scaleable Bandwidth Interconnect (INSBI) The Insert Scaleable Bandwidth Interconnect block maps up to 84 1.544 Mbit/s links, 63 2.048 Mbit/s links, three 44.736 Mbit/s links, three 34.386 Mbit/s links or an arbitary bit rate into the SBI shared bus. The SBI bandwidth is evenly divided into three SPEs, each of which may carry a different payload type. The 1.544 Mbit/s links can be unframed when sourced directly from the DS3 multiplexer or SONET/SDH mapper, or they can be T1 channelized when sourced by the T1 framers. The 2.048 Mbit/s links can be unframed when sourced directly from the SONET/SDH mapper or G.747 demultiplexer, or they can be E1 channelized when sourced by the E1 framers. The 44.736 Mbit/s links and 34.368 Mbit/s links can also be unframed when sourced directly from the DS3/E3 interfaces or from the DS3 mapper. The 44.736 Mbit/s links and 34.368 Mbit/s links can be unchannelized DS3/E3s when sourced from the DS3 or E3 framers. Finally, an arbitrary bandwidth signal that has been received Flexible Bandwidth Port may be output. The SBI Bus Data Formats section provides the details of the mapping formats. Figure 16 Insert SBI
RECEIVER
SD DATA[7:0 ] SDD P SD PL SDV5 SD C1FP SR EFC LK
ELST Elastic Store IN SB I Ingress System Interface
T1/E1 FRM R Framer: Frame A lignment, Alarm Extraction
R JAT D igital Jitter Attenuator
From D S3 Multiplexer or SONET/SD H mapper
Links inserted into the SBI bus can be synchronous to the SBI bus (by setting SYNCH_TRIB=1 in the INSBI Control RAM) or timed from the upstream data source via the sonet/sdh mapper, M13, or DS3/E3 framer. When SYNCH_TRIB is logic 0, the INSBI makes link rate adjustments by adding or deleting an extra byte of data over a 500 mS interval based on buffer fill levels. Timing adjustments are detected by the receiving SBI interface by explicit signals in the SBI bus structure. When SYNCH_TRIB is logic 1, the tributary is "locked" in which no timing adjustments are allowed. The frame slip buffer (ELST) must be in the datapath in "locked" mode. The INSBI always sends valid link rate information across the SBI Drop bus, which contains both ClkRate(1:0) and Phase(3:0) field information. this gives an external device receiving data from the INSBI three methods of creating a
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
recovered link clock: the ClkRate field, the Phase field, or just the rate of data flow across the SBI drop bus. INSBI does not generate the Phase field for DS3/E3 tribs. Channelized T1s inserted into the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s or timeslots. 9.43 Flexible Bandwidth Ports Three Flexible Bandwidth Ports are provided to supply arbitary bandwidth signals to the SBI bus. Each port is associated with one SPE on the SBI bus and may carry up to the capacity of the SPE (48.96 Mbit/s). In the ingress direction, data is presented as a three wire interface: a clock of up to 51.84 MHz, bit serial data and an enable. No flow control is provided, so the average data rate must be less than 48.96 Mbit/s. In the egress direction, a simple handshake controls the data flow. For each cycle that the EFBWDREQ[n] input is high, a bit may be output on the EFBWDAT[n] output. The data is supplied from the SBI bus FIFO, which will be kept half full through the SAJUST_REQ asserts as required. 9.43.1 Burst Lengths on Ingress Flexible Bandwidth Port The SBI bus is capable of transporting flexible bandwidth data up to 48.96 Mbit/s. The SBI interface contains a FIFO for absorbing data bursts in excess of this rate, but there is a limit to the length of the bursts. The limitations are dependent on the IFBWCLK frequency: 1. IFBWCLK < 48.96 MHz: IFBWEN may be high indefinitely. 2. IFBWCLK > 51.5 MHz: IFBWEN may only be high for up to eight consecutive cycles. The DS3 demapper satisfies this constraint when configured to use a 51.84 MHz clock. 3. 48.96 MHz < IFBWCLK < 51.5MHz: The length of the burst is dependent on how much the IFBWCLK frequency exceeds 48.96 MHz, but 256 bits can be buffered before an overflow occurs.
PROPRIETARY AND CONFIDENTIAL
137
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9.44 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The TEMUX-84 identification code is 183160CD hexadecimal.
PROPRIETARY AND CONFIDENTIAL
138
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
9.45 Microprocessor Interface The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the TEMUX-84. The Register Memory Map in Table 9 shows where the normal mode registers are accessed. The resulting register organization splits into sections: Master configuration registers, T1/E1 Framer registers, DS3 M13 multiplexing registers, SONET/SDH mapping registers and SBI registers. On power up reset the TEMUX-84 defaults to 84 T1 framers multiplexed into the three M13 multiplexers using the DS3 M23 multiplex format. For proper operation some register configuration is necessary. System side access defaults to the SBI bus without any tributaries enabled which will leave the SBI Drop bus tristated. By default interrupts will not be enabled, automatic alarm generation is disabled, a dual rail DS3 LIU interface is expected and an external transmit reference clock is required. Table 9 Register Memory Map Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B Revision Global Reset Global Configuration SPE #1 Configuration SPE #2 Configuration SPE #3 Configuration Bus Configuration Global Performance Monitor Update Reference Clock Select Recovered Clock#1 Select Recovered Clock#2 Select Recovered Clock#3 Select Register
PROPRIETARY AND CONFIDENTIAL
139
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x000C 0x000D 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x0020 0x0021 0x0022 0x0023 0x0040 0x0042 0x0043 0x0044 0x0045 0x0046
Register Master H-MVIP Interface Configuration Master Clock Monitor #1 Master Interrupt Source Master Interrupt Source T1E1 Master Interrupt Source SDH #1 Master Interrupt Source SDH #2 Master Interrupt Source SDH #3 Master Interrupt Source SBI Master Interrupt Source DS3/E3 #1 Master Interrupt Source DS2 #1 Master Interrupt Source MX12 #1 Master Interrupt Source DS3/E3 #2 Master Interrupt Source DS2 #2 Master Interrupt Source MX12 #2 Master Interrupt Source DS3/E3 #3 Master Interrupt Source DS2 #3 Master Interrupt Source MX12 #3 Master SBIDET0 Collision Detect LSB Master SBIDET0 Collision Detect MSB Master SBIDET1 Collision Detect LSB Master SBIDET1 Collision Detect MSB T1/E1 Master Configuration T1/E1 PRGD #1 Tributary Select T1/E1 PRGD #2 Tributary Select T1/E1 PRGD #3 Tributary Select T1/E1 PRGD #4 Tributary Select T1/E1 PRGD #5 Tributary Select
PROPRIETARY AND CONFIDENTIAL
140
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0047 0x0048 0x0049 0x004A 0x004C 0x004D 0x004E 0x0050 0x0051 0x0052-0x0056 0x0057 0x0058 - 0x0062 0x0063 0x0064 0x0068 0x0069 0x006A-0x006E 0x006F 0x0070 - 0x007A 0x007B 0x007C 0x0083 0x0084 - 0x008E 0x008F - 0x0099 0x009A 0x00A0 0x00A1
Register T1/E1 PRGD #6 Tributary Select RJAT Indirect Status RJAT Indirect Channel Address Register RJAT Indirect Channel Data Register TJAT Indirect Status TJAT Indirect Channel Address Register TJAT Indirect Channel Data Register RPCC-MVIP Indirect Status/Time-slot Address RPCC-MVIP Indirect Channel Address Register RPCC-MVIP Indirect Channel Data Registers RPCC-MVIP Configuration Bits RPCC-MVIP Interrupt Status RPCC-MVIP PRBS Error Insertion RPCC-MVIP PRBS Error Insert Status RPCC-SBI Indirect Status/Time-slot Address RPCC-SBI Indirect Channel Address Register RPCC-SBI Indirect Channel Data Registers RPCC-SBI Configuration Bits RPCC-SBI Interrupt Status RPCC-SBI PRBS Error Insertion RPCC-SBI PRBS Error Insert Status RX-MVIP-ELST Idle Code RX-MVIP-ELST Slip Status RX-MVIP-ELST Slip Direction RX-MVIP-ELST Slip Interrupt Enable RX-SBI-ELST Indirect Status RX-SBI-ELST Indirect Channel Address Register
PROPRIETARY AND CONFIDENTIAL
141
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x00A2 0x00A3 0x00A4 - 0x00AE 0x00AF - 0x00B9 0x00BA 0x00C0 0x00C1 0x00C2 0x00C4 - 0x00CE 0x00CF - 0x00D9 0x0DA 0x0100 0x0101 0x0102-0x0106 0x0107 0x0108 - 0x0112 0x0113 0x0114 0x0118 0x0119 0x011A - 0x011D 0x011E 0x011F - 0x0129 0x0130 0x0131 0x0132 - 0x0136 0x0137 - 0x0141
Register RX-SBI-ELST Indirect Channel Data Register RX-SBI-ELST Idle Code RX-SBI-ELST Slip Status RX-SBI-ELST Slip Direction RX-SBI-ELST Slip Interrupt Enable TX-ELST Indirect Status TX-ELST Indirect Channel Address Register TX-ELST Indirect Channel Data Register TX-ELST Slip Status TX-ELST Slip Direction TX-ELST Slip Interrupt Enable TPCC Indirect Status/Time-slot Address TPCC Indirect Channel Address Register TPCC Indirect Channel Data Registers TPCC Configuration TPCC Interrupt Status TPCC PRBS Error Insertion TPCC PRBS Error Insert Status RHDL Indirect Status RHDL Indirect Channel Address Register RHDL Indirect Channel Data Registers RHDL Interrupt Control RHDL Interrupt Status THDL Indirect Status THDL Indirect Channel Address Register THDL Indirect Channel Data Registers THDL Interrupt Status
PROPRIETARY AND CONFIDENTIAL
142
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0150 0x0151 0x0152 - 0x0156 0x0157 0x0158 - 0x0162 0x0163 0x0168 0x0169 0x016A - 0x016F 0x0170 0x0171 0x0172 - 0x0186 0x0187 0x0188 - 0x0192 0x01C0 0x01C1 0x01C2 0x01D0 0x01D1 0x01D2 0x01D3 0x01D4 0x01D6 0x01D7 0x01DE 0x01DF 0x01E0
Register SIGX Indirect Status/Time-slot Address SIGX Indirect Channel Address Register SIGX Indirect Channel Data Registers SIGX Configuration Change of Signaling Status Change of Signaling Status Interrupt Enable T1/E1 Transmitter Indirect Status T1/E1 Transmitter Indirect Channel Address T1/E1 Transmitter Indirect Channel Data Registers T1/E1 Framer Indirect Status T1/E1 Framer Indirect Channel Address Register T1/E1 Framer Indirect Channel Data Registers T1/E1 Framer Configuration and Status T1/E1 Framer Interrupt Status SBI Master Reset / Bus Signal Monitor SBI Master Configuration SBI Bus Master Configuration EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Tributary RAM Indirect Access Address EXSBI Tributary RAM Indirect Access Control EXSBI Tributary Control Indirect Access Data SBI Parity Error Interrupt Status EXSBI Depth Check Interrupt Status Extract External ReSynch Interrupt Status INSBI Control
PROPRIETARY AND CONFIDENTIAL
143
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x01E1 0x01E2 0x01E3 0x01E4 0x01E6 0x01E9 0x01EA 0x01F1 0x01F2 0x0200 - 0x2D5 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020C 0x020D 0x020D 0x020E 0x020F 0x0210
Register INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Tributary Indirect Access Address INSBI Tributary Indirect Access Control INSBI Tributary Control Indirect Access Data INSBI T1 Thresholds Register INSBI E1 Thresholds Register INSBI Depth Check Interrupt Status Insert External ReSynch Interrupt Status DS3/E3 Framer and M13 Multiplex #1 DS3 and E3 Master Reset DS3 and E3 Master Data Source DS3 and E3 Master Unchannelized Interface Options DS3/E3 Master Transmit Line Options DS3/E3 Master Receive Line Options DS3/E3 Master Alarm Enable DS2 Master Alarm Enable / DS3 Network Requirement Bit E3 Data Link Control DS3 TRAN Configuration DS3 TRAN Diagnostic DS3 FRMR Configuration DS3 FRMR Interrupt Enable (ACE=0) DS3 FRMR Additional Configuration (ACE=1) DS3 FRMR Interrupt Status DS3 FRMR Status DS3/E3 PMON Performance Meters
PROPRIETARY AND CONFIDENTIAL
144
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0211 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 0x021A 0x021B 0x021C 0x021D 0x021E 0x021F 0x0220 0x0221 0x0222 0x0223 0x0224 0x0225 0x0228 0x0229 0x022A 0x022B 0x022C 0x022D 0x0230
Register DS3/E3 PMON Interrupt Enable/Status DS3/E3 PMON Line Code Violation Event Count LSB DS3/E3 PMON Line Code Violation Event Count MSB DS3/E3 PMON Framing Bit Error Event Count LSB DS3/E3 PMON Framing Bit Error Event Count MSB DS3 PMON Excessive Zeros LSB DS3 PMON Excessive Zeros MSB DS3/E3 PMON Parity Error Event Count LSB DS3/E3 PMON Parity Error Event Count MSB DS3 PMON Path Parity Error Event Count LSB DS3 PMON Path Parity Error Event Count MSB DS3/E3 PMON FEBE Event Count LSB DS3/E3 PMON FEBE Event Count MSB DS3/E3 TDPR Configuration DS3/E3 TDPR Upper Transmit Threshold DS3/E3 TDPR Lower Interrupt Threshold DS3/E3 TDPR Interrupt Enable DS3/E3 TDPR Interrupt Status/UDR Clear DS3/E3 TDPR Transmit Data DS3/E3 RDLC Configuration DS3/E3 RDLC Interrupt Control DS3/E3 RDLC Status DS3/E3 RDLC Data DS3/E3 RDLC Primary Address Match DS3/E3 RDLC Secondary Address Match PRGD Control
PROPRIETARY AND CONFIDENTIAL
145
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0231 0x0232 0x0233 0x0234 0x0238 0x0239 0x023A 0x023B 0x023C 0x023D 0x023E 0x023F 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0248 0x0249 0x024A 0x024B 0x0250 0x0251 0x0252 0x0253
Register PRGD Interrupt Enable/Status PRGD Length PRGD Tap PRGD Error Insertion PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 PRGD Pattern Detector #1 PRGD Pattern Detector #2 PRGD Pattern Detector #3 PRGD Pattern Detector #4 MX23 Configuration MX23 Demux AIS Insert MX23 Mux AIS Insert MX23 Loopback Activate MX23 Loopback Request Insert MX23 Loopback Request Detect MX23 Loopback Request Interrupt FEAC XBOC Control FEAC XBOC Code FEAC RBOC Configuration/Interrupt Enable FEAC RBOC Interrupt Status DS2 FRMR #1 Configuration DS2 FRMR #1 Interrupt Enable DS2 FRMR #1 Interrupt Status DS2 FRMR #1 Status
PROPRIETARY AND CONFIDENTIAL
146
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x0260 0x0268 0x0270 0x0278 0x0280 0x0288 0x0290 0x0298 0x02A0 0x02A8 0x02B0 0x02B8 0x02C0 0x02C1 0x02C2 0x02C3 0x02C4 0x02C5
Register DS2 FRMR #1 Monitor Interrupt Enable/Status DS2 FRMR #1 FERR Count DS2 FRMR #1 PERR Count (LSB) DS2 FRMR #1 PERR Count (MSB) MX12 #1Configuration and Control MX12 #1 Loopback Code Select MX12 #1 Mux/Demux AIS Insert MX12 #1 Loopback Activate MX12 #1 Loopback Interrupt DS2 FRMR #2 Registers MX12 #2 Registers DS2 FRMR #3 Registers MX12 #3 Registers DS2 FRMR #4 Registers MX12 #4 Registers DS2 FRMR #5 Registers MX12 #5 Registers DS2 FRMR #6 Registers MX12 #6 Registers DS2 FRMR #7 Registers MX12 #7 Registers E3 FRMR Framing Options E3 FRMR Maintenance Options E3 FRMR Framing Interrupt Enable E3 FRMR Framing Interrupt Indication and Status E3 FRMR Maintenance Event Interrupt Enable E3 FRMR Maintenance Event Interrupt Indication
PROPRIETARY AND CONFIDENTIAL
147
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x02C6 0x02C8 0x02C9 0x02CA 0x02CB 0x02D0 0x02D1 0x02D2 0x02D3 0x02D4 0x02D5 0x0300 - 0x03D5 0x0400 - 0x04D5 0x0500, 0x0520, 0x0540, 0x0560, 0x0580, 0x05A0 0x0501, 0x0521, 0x0541, 0x0561, 0x0581, 0x05A1 0x0502, 0x0522, 0x0542, 0x0562, 0x0582, 0x05A2 0x0503, 0x0523, 0x0543, 0x0563, 0x0583, 0x05A3 0x0504, 0x0524, 0x0544, 0x0564, 0x0584, 0x05A4 0x0508, 0x0528, 0x0548, 0x0568, 0x0588, 0x05A8
Register E3 FRMR Maintenance Event Status E3 TRAN Framing Options E3 TRAN Status and Diagnostic Options E3 TRAN BIP-8 Error Mask E3 TRAN Maintenance and Adaptation Options TTB Control TTB Trail Trace Identifier Status TTB Indirect Address TTB Indirect Data TTB Expected Payload Type Label TTB Payload Type Label Control/Status DS3/E3 Framer and M13 Multiplex #2 DS3/E3 Framer and M13 Multiplex #3 T1/E1 Pattern Generator and Detector Control
T1/E1 Pattern Generator and Detector Interrupt Enable/Status T1/E1 Pattern Generator and Detector Length
T1/E1 Pattern Generator and Detector Tap
T1/E1 Pattern Generator and Detector Error Insertion T1/E1 Pattern Generator and Detector Pattern Insertion #1
PROPRIETARY AND CONFIDENTIAL
148
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0509, 0x0529, 0x0549, 0x0569, 0x0589, 0x05A9 0x050A, 0x052A, 0x054A, 0x056A, 0x058A, 0x05AA 0x050B, 0x052B, 0x054B, 0x056B, 0x058B, 0x05AB 0x050C, 0x052C, 0x054C, 0x056C, 0x058C, 0x05AC 0x050D, 0x052D, 0x054D, 0x056D, 0x058D, 0x05AD 0x050E, 0x052E, 0x054E, 0x056E, 0x058E, 0x05AE 0x050F, 0x052F, 0x054F, 0x056F, 0x058F, 0x05AF 0x0510, 0x0530, 0x0550, 0x0570, 0x0590, 0x05B0 0x0511, 0x0531, 0x0551, 0x0571, 0x0591, 0x05B1 0x0512, 0x0532, 0x0552, 0x0572, 0x0592, 0x05B2 0x0513, 0x0533, 0x0553, 0x0533, 0x0593, 0x05B3
Register T1/E1 Pattern Generator and Detector Pattern Insertion #2 T1/E1 Pattern Generator and Detector Pattern Insertion #3 T1/E1 Pattern Generator and Detector Pattern Insertion #4 T1/E1 Pattern Generator and Detector Pattern Detector #1 T1/E1 Pattern Generator and Detector Pattern Detector #2 T1/E1 Pattern Generator and Detector Pattern Detector #3 T1/E1 Pattern Generator and Detector Pattern Detector #4 Generator Controller Configuration
Generator Controller P Access Status
Generator Controller Channel Indirect Address/Control Generator Controller Channel Indirect Data Buffer
PROPRIETARY AND CONFIDENTIAL
149
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0514, 0x0534, 0x0554, 0x0574, 0x0594, 0x05B4 0x0515, 0x0535, 0x0555, 0x0575, 0x0595, 0x05B5 0x0516, 0x0536, 0x0556, 0x0576, 0x0596, 0x05B6 0x0517, 0x0537, 0x0557, 0x0577, 0x0597, 0x05B7 0x0700 0x0701 0x0702 0x0703 0x0704 0x0705 0x0706 0x0707 0x0708 0x0709 0x070A 0x070B 0x070C 0x070D
Register Receiver Controller Configuration
Receiver Controller P Access Status
Receiver Controller Channel Indirect Address/Control Receiver Controller Channel Indirect Data Buffer
SONET/SDH Master Reset SONET/SDH Master Ingress Configuration SONET/SDH Master Egress Configuration SONET/SDH Master Ingress VTPP Configuration SONET/SDH Master Egress VTPP Configuration SONET/SDH Master RTOP Configuration SONET/SDH Master Tributary Alarm AIS Control SONET/SDH Master Tributary Remote Defect Indication Control SONET/SDH Master Tributary Auxiliary Remote Defect Indication Control SONET/SDH Master DS3/E3 Clock Generation Control SONET/SDH Master Loopback Control SONET/SDH Telecom Bus Signal Monitor, Accumulation Trigger SONET/SDH Transmit Pointer Configuration #1 (MSB) SONET/SDH Transmit Pointer Configuration #2 (LSB)
PROPRIETARY AND CONFIDENTIAL
150
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x740 - 0x077F 0x0740, 0x0742, 0x0744, 0x0746, 0x0748, 0x074A, 0x074C 0x0741, 0x0743, 0x0745, 0x0747, 0x0749, 0x074B, 0x074D 0x074E 0x074F 0x0750, 0x0752, 0x0754, 0x0756, 0x0758, 0x075A, 0x075C 0x0751, 0x0753, 0x0755, 0x0757, 0x0759, 0x075B, 0x075D 0x075E 0x075F 0x0760, 0x0762, 0x0764, 0x0766, 0x0768, 0x076A, 0x076C 0x0761, 0x0763, 0x0765, 0x0767, 0x0769, 0x076B, 0x076D 0x076E Ingress VTPP #1
Register
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress, TU #1 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress, TU #2 in TUG2 #1 to TUG2 #7 AIS Interrupt VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt
PROPRIETARY AND CONFIDENTIAL
151
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x076F 0x0770, 0x0772, 0x0774, 0x0776, 0x0778, 0x077A, 0x077C 0x0771, 0x0773, 0x0775, 0x0777, 0x0779, 0x077B, 0x077D 0x077E 0x077F 0x780 - 0x07BF 0x7C0 - 0x07FF 0x0800 - 0x85E 0x0860 0x0862 0x0863 0x0864 0x0865 0x0900 - 0x93F 0x0900, 0x0902, 0x0904, 0x0906, 0x0908, 0x090A, 0x090C 0x0901, 0x0903, 0x0905, 0x0907, 0x0909, 0x090B, 0x090D
Register VTPP Ingress, TU #3 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress, TU #4 in TUG2 #1 to TUG2 #7, AIS Interrupt Ingress VTPP #2 Ingress VTPP #3 RTDM Tributary Control Reserved RTDM Time Switch Page Control RTDM Indirect Time Switch Tributary RAM Status and Control RTDM Indirect Time Switch Internal Link Address RTDM Indirect Ingress Tributary Data Egress VTPP #1 VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, Alarm Status
PROPRIETARY AND CONFIDENTIAL
152
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x090E 0x090F 0x0910, 0x0912, 0x0914, 0x0916, 0x0918, 0x091A, 0x091C 0x0911, 0x0913, 0x0915, 0x0917, 0x0919, 0x091B, 0x091D 0x091E 0x091F 0x0920, 0x0922, 0x0924, 0x0926, 0x0928, 0x092A, 0x092C 0x0921, 0x0923, 0x0925, 0x0927, 0x0929, 0x092B, 0x092D 0x092E 0x092F 0x0930, 0x0932, 0x0934, 0x0936, 0x0938, 0x093A, 0x093C
Register VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #1 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #2 in TUG2 #1 to TUG2 #7 AIS Interrupt VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #3 in TUG2 #1 to TUG2 #7, AIS Interrupt VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status
PROPRIETARY AND CONFIDENTIAL
153
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0931, 0x0933, 0x0935, 0x0937, 0x0939, 0x093B, 0x093D 0x093E 0x093F 0x0940 - 0x97F 0x0980 - 0x9BF 0x09C0 0x09C3 0x09C4 0x09C5 0x09C6 0x09E0 0x09E3 0x09E4 0x09E5 0x09E6 0x0x9EF
Register VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, Alarm Status
VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress, TU #4 in TUG2 #1 to TUG2 #7, AIS Interrupt Egress VTPP #2 Egress VTPP #3 Byte Synchronous Mapping Control Register Byte Synchronous Mapping Tributary Indirect Access Address Register Byte Synchronous Mapping Tributary Indirect Access Control Register Byte Synchronous Mapping Tributary Mapping Indirect Access Data Register Byte Synchronous Mapping Tributary Control Indirect Access Data Register Byte Synchronous Demapping Control Register Byte Synchronous Demapping Tributary RAM Indirect Access Address Register Byte Synchronous Demapping Tributary RAM Indirect Access Control Register Byte Synchronous Demapping Tributary Mapping RAM Indirect Access Data Register Byte Synchronous Demapping Tributary Control RAM Indirect Access Data Register Byte Synchronous Demapping FIFO Control Register
0x0A00 - 0x0AFD Receive Tributary Overhead Processor (RTOP) #1
PROPRIETARY AND CONFIDENTIAL
154
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0A00, 0x0A08, 0x0A10, 0x0A18, 0x0A20, 0x0A28, 0x0A30 0x0A01, 0x0A09, 0x0A11, 0x0A19, 0x0A21, 0x0A29, 0x0A31 0x0A02, 0x0A0A, 0x0A12, 0x0A1A, 0x0A22, 0x0A2A, 0x0A32 0x0A03, 0x0A0B, 0x0A13, 0x0A1B, 0x0A23, 0x0A2B, 0x0A33 0x0A04, 0x0A0C, 0x0A14, 0x0A1C, 0x0A24, 0x0A2C, 0x0A34 0x0A05, 0x0A0D, 0x0A15, 0x0A1D, 0x0A25, 0x0A2D, 0x0A35 0x0A06, 0x0A0E, 0x0A16, 0x0A1E, 0x0A26, 0x0A2E, 0x0A36 0x0A07, 0x0A0F, 0x0A17, 0x0A1F, 0x0A27, 0x0A2F, 0x0A37 0x0A38 0x0A39
Register RTOP, TU #1 in TUG2 #1 to TUG2 #7, Configuration
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
RTOP, TU #1 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
RTOP, TU #1 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
RTOP, TU #1 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
RTOP, TU #1 in TUG2 #2 to TUG2 #7, FEBE Error Count LSB
RTOP, TU #1 in TUG2 #2 to TUG2 #7, FEBE Error Count MSB
RTOP, TU #1 in TUG2 #1 to TUG2 #7, COPSL Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7, PSLM Interrupt
PROPRIETARY AND CONFIDENTIAL
155
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0A3A 0x0A3B 0x0A3C 0x0A3D 0x0A40, 0x0A48, 0x0A50, 0x0A58, 0x0A60, 0x0A68, 0x0A70 0x0A41, 0x0A49, 0x0A51, 0x0A59, 0x0A61, 0x0A69, 0x0A71 0x0A42, 0x0A4A, 0x0A52, 0x0A5A, 0x0A62, 0x0A6A, 0x0A72 0x0A43, 0x0A4B, 0x0A53, 0x0A5B, 0x0A63, 0x0A6B, 0x0A73 0x0A44, 0x0A4C, 0x0A54, 0x0A5C, 0x0A64, 0x0A6C, 0x0A74 0x0A45, 0x0A4D, 0x0A55, 0x0A5D, 0x0A65, 0x0A6D, 0x0A75 0x0A46, 0x0A4E, 0x0A56, 0x0A5E, 0x0A66, 0x0A6E, 0x0A76
Register RTOP, TU #1 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7, RDI Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7 RFI Interrupt RTOP, TU #1 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP, TU #2 in TUG2 #1 to TUG2 #7, Configuration
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
RTOP, TU #2 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
RTOP, TU #2 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
RTOP, TU #2 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
RTOP, TU #2 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
PROPRIETARY AND CONFIDENTIAL
156
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0A47, 0x0A4F, 0x0A57, 0x0A5F, 0x0A67, 0x0A6F, 0x0A77 0x0A78 0x0A79 0x0A7A 0x0A7B 0x0A7C 0x0A7D 0x0A80, 0x0A88, 0x0A90, 0x0A98, 0x0AA0, 0x0AA8, 0x0AB0 0x0A81, 0x0A89, 0x0A91, 0x0A99, 0x0AA1, 0x0AA9, 0x0AB1 0x0A82, 0x0A8A, 0x0A92, 0x0A9A, 0x0AA2, 0x0AAA, 0x0AB2 0x0A83, 0x0A8B, 0x0A93, 0x0A9B, 0x0AA3, 0x0AAB, 0x0AB3 0x0A84, 0x0A8C, 0x0A94, 0x0A9C, 0x0AA4, 0x0AAC, 0x0AB4
Register RTOP, TU #2 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
RTOP, TU #2 in TUG2 #1 to TUG2 #7, COPSL Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, RDI Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, RFI Interrupt RTOP, TU #2 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP, TU #3 in TUG2 #1 to TUG2 #7, Configuration
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
RTOP, TU #3 in TUG2 #1 to TUG2 #7, Accepted Path Signal Label
RTOP, TU #3 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
PROPRIETARY AND CONFIDENTIAL
157
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0A85, 0x0A8D, 0x0A95, 0x0A9D, 0x0AA5, 0x0AAD, 0x0AB5 0x0A86, 0x0A8E, 0x0A96, 0x0A9E, 0x0AA6, 0x0AAE, 0x0AB6 0x0A87, 0x0A8F, 0x0A97, 0x0A9F, 0x0AA7, 0x0AAF, 0x0AB7 0x0AB8 0x0AB9 0x0ABA 0x0ABB 0x0ABC 0x0ABD 0x0AC0, 0x0AC8, 0x0AD0, 0x0AD8, 0x0AE0, 0x0AE8, 0x0AF0 0x0AC1, 0x0AC9, 0x0AD1, 0x0AD9, 0x0AE1, 0x0AE9, 0x0AF1 0x0AC2, 0x0ACA, 0x0AD2, 0x0ADA, 0x0AE2, 0x0AEA, 0x0AF2
Register RTOP, TU #3 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
TU #3 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
RTOP, TU #3 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
RTOP, TU #3 in TUG2 #1 to TUG2 #7, COPSL Interrupt RTOP, TU #3 in TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP, TU #3 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #3 in TUG2 #1 to TUG2 #7, RDI Interrupt RTOP, TU #3 in TUG2 #1 to TUG2 #7, RFI Interrupt RTOP, TU #3 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP, TU #4 in TUG2 #1 to TUG2 #7, Configuration
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
PROPRIETARY AND CONFIDENTIAL
158
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0AC3, 0x0ACB, 0x0AD3, 0x0ADB, 0x0AE3, 0x0AEB, 0x0AF3 0x0AC4, 0x0ACC, 0x0AD4, 0x0ADC, 0x0AE4, 0x0AEC, 0x0AF4 0x0AC5, 0x0ACD, 0x0AD5, 0x0ADD, 0x0AE5, 0x0AED, 0x0AF5 0x0AC6, 0x0ACE, 0x0AD6, 0x0ADE, 0x0AE6, 0x0AEE, 0x0AF6 0x0AC7, 0x0ACF, 0x0AD7, 0x0ADF, 0x0AE7, 0x0AEF, 0x0AF7 0x0AF8 0x0AF9 0x0AFA 0x0AFB 0x0AFC 0x0AFD
Register RTOP, TU #4 in TUG2 #1 to TUG2 #7, Path Signal Label
RTOP, TU #4 in TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, FEBE Error Count LSB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, FEBE Error Count MSB
RTOP, TU #4 in TUG2 #1 to TUG2 #7, COPSL Interrupt RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP, TU #4 in TUG2 #1 to TUG2 #7, RDI Interrupt RTOP, TU #4 in TUG2 #1 to TUG2 #7, RFI Interrupt RTOP, TU #4 in TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration
0x0B00 - 0x0BFD Receive Tributary Overhead Processor (RTOP) #2 0x0C00 - 0x0CFD Receive Tributary Overhead Processor (RTOP) #3
PROPRIETARY AND CONFIDENTIAL
159
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0D00 - 0x0D06 0x0D07 0x0D08 - 0x0D0E 0x0D0F 0x0D10 - 0x0D16 0x0D17 0x0D18 - 0x0D1E 0x0D1F 0x0D20 - 0x0D26 0x0D27 0x0D28 - 0x0D2E 0x0D2F 0x0D30 - 0x0D36 0x0D37 0x0D38 - 0x0D3E 0x0D3F
Register TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1 Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control
PROPRIETARY AND CONFIDENTIAL
160
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0D40 - 0x0D46 0x0D47 0x0D48 - 0x0D4E 0x0D4F 0x0D50 - 0x0D56 0x0D57 0x0D58 - 0x0D5E 0x0D5F 0x0D60 0x0D61 0x0D62 0x0D63 0x0D68 0x0D69- 0x0D6E 0x0D70 - 0x0D76 0x0D78 - 0x0D7E 0x0D80 0x0D81 - 0x0D86
Register TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TRAP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP Indirect Remote Alarm Page Address TRAP Indirect Remote Alarm Tributary Address TRAP Indirect Datapath Tributary Data TRAP RDI Control TRAP Remote Parallel Alarm Port TUG2 #1 of TUG3 #1 Configuration TRAP Remote Parallel Alarm Port TUG2 #2 to TUG2 #7 of TUG3 #1 Configuration TRAP Remote Parallel Alarm Port TUG2 #1 to TUG2 #7 of TUG3 #2 Configuration TRAP Remote Parallel Alarm Port TUG2 #1 to TUG2 #7 of TUG3 #3 Configuration TTOP TU #1 in TUG2 #1 of TUG3 #1, Control TTOP TU #1 in TUG2 #2 to TUG2 #7 of TUG3 #1, Control
PROPRIETARY AND CONFIDENTIAL
161
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0D87 0x0D88 - 0x0D8E 0x0D8F 0x0D90 - 0x0D96 0x0D97 0x0D98 - 0x0D9E 0x0D9F 0x0DA0 - 0x0DA6 0x0DA7 0x0DA8 - 0x0DAE 0x0DAF 0x0DB0 - 0x0DB6 0x0DB7 0x0DB8 - 0x0DBE 0x0DBF 0x0DC0 - 0x0DC6 0x0DC7
Register TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #1 BIP Diagnostic Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #1 BIP Diagnostic Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #1, BIP Diagnostic Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #1, BIP Diagnostic Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #1 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control
PROPRIETARY AND CONFIDENTIAL
162
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0DC8 - 0x0DCE 0x0DCF 0x0DD0 - 0x0DD6 0x0DD7 0x0DD8 - 0x0DDE 0x0DDF 0x0DE0 0x0DE1 0x0DE2 0x0DE4 0x0DE5 0x0DE6 0x0DE7 0x0E00 - 0x0E5E 0x0E61 0x0E62 0x0E63 0x0E64 0x0E65 0x0E80 - 0x0E82 0x0E80 0x0E81 0x0E82
Register TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #2 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #3 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, Control TTOP TU #4 in TUG2 #1 to TUG2 #7 of TUG3 #3, BIP Diagnostic Control TTOP TUG3 #1 Control TTOP TUG3 #2 Control TTOP TUG3 #3 Control TTOP Trail Trace Identifier Page Select TTOP Indirect Trail Trace Identifier Tributary Select TTOP Indirect Trail Trace Identifier Buffer Address TTOP Indirect Trail Trace Identifier Buffer Data TTMP Tributary Control TTMP Time Switch Page Control TTMP Indirect Time Switch RAM Control and Status TTMP Indirect Egress Tributary Address TTMP Indirect Time Switch Internal Link Data TTMP Telecom Interface Configuration D3MD #1 D3MD Control D3MD Interrupt Status D3MD Interrupt Enable
PROPRIETARY AND CONFIDENTIAL
163
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0E84 - 0x0E86 0x0E88 - 0x0E8A 0x0E8C - 0x0E8E 0x0E8C 0x0E8D 0x0E8E 0x0E90 - 0x0E92 0x0E94 - 0x0E96 0x0F00 - 0x0F2B 0x0F00 0x0F01 to 0x0F06 0x0F08 to 0x0F0E 0x0F10H to 0x0F16 0x0F18 to 0x0F1E 0x0F20 + 0x40*N 0x0F21 0x0F22 0x0F23 0x0F24 0x0F25 0x0F26 0x0F27 0x0F28 D3MD #2 D3MD #3 D3MA #1 D3MA Control
Register
D3MA Interrupt Status D3MA Interrupt Enable D3MA #2 D3MA #3 RTTB #1 RTTB TU3 or TU #1 in TUG2 #1, Configuration and Status RTTB TU #1 in TUG2 #2 to TUG2 #7, Configuration and Status RTTB TU #2 in TUG2 #1 to TUG2 #7, Configuration and Status RTTB TU #3 in TUG2 #1 to TUG2 #7, Configuration and Status RTTB TU #4 in TUG2 #1 to TUG2 #7, Configuration and Status RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIM Interrupt RTTB TU #2 in TUG2 #1 to TUG2 #7, TIM Interrupt RTTB TU #3 in TUG2 #1 to TUG2 #7, TIM Interrupt RTTB TU #4 in TUG2 #1 to TUG2 #7, TIM Interrupt RTTB TU3 or TU #1 in TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TU #2 in TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TU #3 in TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TU #4 in TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TIU Threshold
PROPRIETARY AND CONFIDENTIAL
164
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Address 0x0F29 0x0F2A 0x0F2B 0x0F40 - 0x0F6B 0x0F80 - 0x0FAB 0x1000
Register RTTB Indirect Tributary Select RTTB Indirect Address Select RTTB Indirect Data Select RTTB #2 RTTB #3 Master Test
For all register accesses, CSB must be low.
PROPRIETARY AND CONFIDENTIAL
165
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the TEMUX-84. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[12]) is low. The register descriptions are contained in a separate TEMUX-84 register description document. Notes on Normal Mode Register Bits: 1) Writing values into unused register bits typically has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bit must be written with logic 0. Reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2) All configuration bits that can be written into can also be read back. This allows the processor controlling the TEMUX-84 to determine the programming state of the block. 3) Writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4) Writing into read-only normal mode register bit locations does not affect TEMUX-84 operation unless otherwise noted.
PROPRIETARY AND CONFIDENTIAL
166
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
11
TEST FEATURES DESCRIPTION The TEMUX-84 contains test features for both production testing and board testing. Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the TEMUX-84. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[12]) is high. Notes on Register Bits: 1) Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. 2) Writeable register bits are not initialized upon reset unless otherwise noted.
PROPRIETARY AND CONFIDENTIAL
167
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Register 0x1000: Master Test Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W W R/W W R/W Type R/W Function Reserved Unused Unused PMCTST DBCTRL Reserved HIZDATA HIZIO Default 0 X X 0 X 0 X 0
This register is used to select TEMUX-84 test features. All bits, except for PMCTST, are reset to zero by a hardware reset of the TEMUX-84; a software reset of the TEMUX-84 does not affect the state of the bits in this register. PMCTST: The PMCTST bit is used to configure the TEMUX-84 for PMC's manufacturing tests. When PMCTST is set to logic 1, the TEMUX-84 microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit can only be cleared by setting CSB to logic 1. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin while PMCTST is a logic 1. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the TEMUX-84 to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. When PMCTST is logic 0, the DBCTRL bit is ignored. Reserved These bits must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL
168
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
HIZIO: The HIZIO bit controls the tri-state modes of the output pins of the TEMUX84. While the HIZIO bit is a logic 1, all output pins of the TEMUX-84, except the data bus, are held in a high-impedance state. The microprocessor interface is still active. HIZDATA: The HIZDATA bit controls the tri-state modes of the TEMUX-84. While the HIZIO bit is a logic 1, all output pins of the TEMUX-84, except the data bus, are held in a high-impedance state. While the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
PROPRIETARY AND CONFIDENTIAL
169
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
11.1 JTAG Test Port The TEMUX-84 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Table 10 Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Table 11 Identification Register Length Version number Part Number Manufacturer's identification code Device identification 32 bits 0x0 0x8316 0x0CD 0x083160CD
PROPRIETARY AND CONFIDENTIAL
170
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
The boundary scan register is made up of 302 boundary scan cells, divided into input observation (IN_CELL), output (OUT_CELL) and bidirectional (IO_CELL) cells. These cells are detailed in the following pages. The first 32 cells form the ID code register and carry the code 083160CDH. The boundary scan chain order is presented in Table 12. Table 12 Boundary Scan Register
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
SDC1FP_MVID_1 OEB_SDC1FP_MVID_1 SBIACT_MVID_2 OEB_SBIACT_MVID_2 SAJUST_REQ_MVID_3 OEB_SAJUST_REQ_ MVID_3 SDDATA_0_MVID_4 OEB_SDDATA_0_MVID_4 SDDATA_1_MVID_5 OEB_SDDATA_1_MVID_5 SDDATA_2_MVID_6 OEB_SDDATA_2_MVID_6 SDDATA_3_MVID_7 OEB_SDDATA_3_MVID_7 SDDATA_4_MVID_8 OEB_SDDATA_4_MVID_8 SDDATA_5_MVID_9 OEB_SDDATA_5_MVID_9 SDDATA_6_MVID_10 OEB_SDDATA_6_MVID_10 SDDATA_7_MVID_11 OEB_SDDATA_7_MVID_11 SDDP_MVID_12 OEB_SDDP_MVID_12
0 1 2 3 4 5
IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OEB_D_3 D_4 OEB_D_4 D_5 OEB_D_5 D_6
151 152 153 154 155 156
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
-
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OEB_D_6 D_7 OEB_D_7 ALE RSTB A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174
OUT_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
SDPL_MVID_13 OEB_SDPL_MVID_13 SDV5_MVID_14 OEB_SDV5_MVID_14 MVID_15 OEB_MVID_15 MVID_16 OEB_MVID_16 MVID_17 OEB_MVID_17 MVID_18 OEB_MVID_18 MVID_19 OEB_MVID_19 MVID_20 OEB_MVID_20 MVID_21 OEB_MVID_21 SREFCLK MVED_1 MVED_2 S77_MVED_3 SAC1FP_MVED_4 SADATA_0_MVED_5 SADATA_1_MVED_6 SADATA_2_MVED_7 SADATA_3_MVED_8 SADATA_4_MVED_9 SADATA_5_MVED_10 SADATA_6_MVED_11 SADATA_7_MVED_12 SADP_MVED_13
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
WRB RDB CSB LAV5 OEB_LAV5 LAPL OEB_LAPL LADP OEB_LADP LADATA_0 OEB_LADATA_0 LADATA_1 OEB_LADATA_1 LADATA_2 OEB_LADATA_2 LADATA_3 OEB_LADATA_3 LADATA_4 OEB_LADATA_4 LADATA_5 OEB_LADATA_5 LADATA_6 OEB_LADATA_6 LADATA_7 OEB_LADATA_7 LAOE/LATPL OEB_LAOE LAC1J1V1 OEB_LAC1J1V1 LAC1 CLK52M RADWEST
175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL
-
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
SAPL_MVED_14 SAV5_MVED_15 SBIDET_0_MVED_16 SBIDET_1_MVED_17 MVED_18 TS0ID OEB_TS0ID MVED_19 MVED_20 MVED_21 CCSID_1 OEB_CCSID_1 CCSID_2 OEB_CCSID_2 CCSID_3 OEB_CCSID_3 EFBWEN_1_CASID_1 OEB_EFBWEN_1_CASID_1 EFBWDAT_1_CASID_2 OEB_EFBWDAT_1_ CASID_2 CASID_3 OEB_CASID_3 CASID_4 OEB_CASID_4 CASID_5 OEB_CASID_5 CASID_6 OEB_CASID_6 CASID_7 OEB_CASID_7 EFBWEN_2_CASID_8
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
RADWESTFP RADWESTCK RADEAST RADEASTFP RADEASTCK LDAIS LDTPL LDV5 LDPL LDC1J1V1 LDDP LDDATA_0 LDDATA_1 LDDATA_2 LDDATA_3 LDDATA_4 LDDATA_5 LDDATA_6 LDDATA_7 L77
207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
76 77 78 79 80 81 82 83 84 85 86
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
LREFCLK TNEG_TMFP_1 OEB_TNEG_TMFP_1 TCLK_1 OEB_TCLK_1 TPOS_TDAT_1 OEB_TPOS_TDAT_1 TICLK_1 RNEG_RLCV_1 RPOS_RDAT_1 RCLK_1
227 228 229 230 231 232 233 234 235 236 237
IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
OEB_EFBWEN_2_CASID_8 EFBWDAT_2_CASID_9 OEB_EFBWDAT_2_ CASID_9 CASID_10 OEB_CASID_10 CASID_11 OEB_CASID_11 CASID_12 OEB_CASID_12 CASID_13 OEB_CASID_13 CASID_14 OEB_CASID_14 EFBWEN_3_CASID_15 OEB_EFBWEN_3_ CASID_15 EFBWDAT_3_CASID_16 OEB_EFBWDAT_3_ CASID_16 CASID_17 OEB_CASID_17 CASID_18 OEB_CASID_18 CASID_19 OEB_CASID_19 CASID_20 OEB_CASID_20 CASID_21 OEB_CASID_21 CTCLK CCSED_1
87 88 89
OUT_CELL OUT_CELL OUT_CELL
-
TNEG_TMFP_2 OEB_TNEG_TMFP_2 TCLK_2
238 239 240
OUT_CELL OUT_CELL OUT_CELL
-
90 91 92 93 94 95 96 97 98 99 100 101
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
OEB_TCLK_2 TPOS_TDAT_2 OEB_TPOS_TDAT_2 TICLK_2 RNEG_RLCV_2 RPOS_RDAT_2 RCLK_2 TNEG_TMFP_3 OEB_TNEG_TMFP_3 TCLK_3 OEB_TCLK_3 TPOS_TDAT_3
241 242 243 244 245 246 247 248 249 250 251 252
OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
102 103
OUT_CELL OUT_CELL
-
OEB_TPOS_TDAT_3 TICLK_3
253 254
OUT_CELL IN_CELL
-
104 105 106 107 108 109 110 111 112 113 114 115
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL
-
RNEG_RLCV_3 RPOS_RDAT_3 RCLK_3 RGAPCLK_RSCLK_1 OEB_RGAPCLK_RSCLK_1 RDATO_1 OEB_RDATO_1 ROVRHD_1 OEB_ROVRHD_1 RFPO_RMFPO_1 OEB_RFPO_RMFPO_1 TFPO_TMFPO_ TGAPCLK_1
255 256 257 258 259 260 261 262 263 264 265 266
IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
-
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
CCSED_2
116
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_1
267
OUT_CELL
-
CCSED_3 IFBWCLK_1_CASED_1 IFBWDAT_1_CASED_2 IFBWEN_1_CASED_3 EFBWCLK_1_CASED_4 EFBWDREQ_1_CASED_5 CASED_6 CASED_7 IFBWCLK_2_CASED_8 IFBWDAT_2_CASED_9 IFBWEN_2_CASED_10
117 118 119 120 121 122 123 124 125 126 127
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
TFPI_TMFPI_1 TDATI_1 RGAPCLK_RSCLK_2 OEB_RGAPCLK_RSCLK_2 RDATO_2 OEB_RDATO_2 ROVRHD_2 OEB_ROVRHD_2 RFPO_RMFPO_2 OEB_RFPO_RMFPO_2 TFPO_TMFPO_TGAPCLK_ 2
268 269 270 271 272 273 274 275 276 277 278
IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
1 0 1 1 0 0 1 1 0
EFBWCLK_2_CASED_11
128
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_2
279
OUT_CELL
0
EFBWDREQ_2_CASED_12 CASED_13 CASED_14 IFBWCLK_3_CASED_15 IFBWDAT_3_CASED_16 IFBWEN_3_CASED_17 EFBWCLK_3_CASED_18 EFBWDREQ_3_CASED_19 CASED_20 CASED_21 CMVFPB
129 130 131 132 133 134 135 136 137 138 139
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
-
TFPI_TMFPI_2 TDATI_2 RGAPCLK_RSCLK_3 OEB_RGAPCLK_RSCLK_3 RDATO_3 OEB_RDATO_3 ROVRHD_3 OEB_ROVRHD_3 RFPO_RMFPO_3 OEB_RFPO_RMFPO_3 TFPO_TMFPO_ TGAPCLK_3
280 281 282 283 284 285 286 287 288 289 290
IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
0 0 0 1 1 0 1 0 0 0 1
CMVFPC
140
IN_CELL
-
OEB_TFPO_TMFPO_ TGAPCLK_3
291
OUT_CELL
1
CMV8MCLK INTB OEB_INTB
141 142 143
IN_CELL OUT_CELL OUT_CELL
-
TFPI_TMFPI_3 TDATI_3 RECVCLK_3
292 293 294
IN_CELL IN_CELL OUT_CELL
0 0 0
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Pin/ Enable
Bit #
Cell Type
Id Bit
Pin/ Enable
Bit #
Cell Type
Id Bit
D_0 OEB_D_0 D_1 OEB_D_1 D_2 OEB_D_2 D_3
144 145 146 147 148 149 150
IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
-
OEB_RECVCLK_3 RECVCLK_2 OEB_RECVCLK_2 RECVCLK_1 OEB_RECVCLK_1 XCLK_E1 XCLK_T1
295 296 297 298 299 300 301
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL
0 0 1 0 0 0 0
NOTES: 1. Register bit 301 is the first bit of the scan chain (closest to TDI). 2. Enable cell OEB_pinname, sets ball pinname to high-impedance when set high.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
12
OPERATION
12.1 Tributary Indexing The TEMUX-84 is capable of transporting 84 1.544 Mbit/s (T1) or 63 2.048 Mbit/s (E1) tributaries. This section explains the correspondence between the indexing systems of the various mapping and multiplexing formats: SBI Bus, Telecom Bus, M13 and H-MVIP. The listed index systems are used throughout the document. The SBI Bus tributary designation uses two integers: the first represents the byte interleaved SPE number (range 1 to 3) and the second is the link index within the SPE (range 1 to 28). The Telecom Bus indexing follows the conventions of the ITU-T multiplexing structure. The bandwidth is divided into three TUG-3s numbered 1 through 3, each of which is composed of seven TUG-2s numbered 1 through 7, each of which is composed of either three TU-12s numbered 1 through 3 or four TU-11s numbered 1 through 4. The three DS3s are divided into seven DS2s, each of which is composed of either four 1.544 Mbit/s or three 2.048 Mbit/s tributaries. The payload capacity is divided into three equal portions. Each of the following lists represents one set of equivalent tributaries: * * * SPE #1, TUG-3 #1, DS3 #1 and MVID/MVED[1:7] SPE #2, TUG-3 #2, DS3 #2 and MVID/MVED[8:14] SPE #3, TUG-3 #3, DS3 #3 and MVID/MVED[15:21]
Table 13 and Table 14 provide the equivalencies between the various multiplex and mapping formats. Alternately, the formats can be equated with the following formulae: 1.544Mbit/s SBI LINK # = 7*(TU11-1) + TUG2 = 4*(DS2-1)+DS1 = 4*(MVED index - 7*SPE - 1) + DS1 = 7*(TU12-1) + TUG2 = 3*(DS2-1)+E1 = 4*(MVED index - 7*SPE - 1) + E1
2.048Mbit/s SBI LINK #
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 13 Indexing for 1.544 Mbit/s Tributaries
SBI Bus SPE, LINK 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 2,1 ... Telecom Bus TUG-3, TUG-2, TU11 1,1,1 1,2,1 1,3,1 1,4,1 1,5,1 1,6,1 1,7,1 1,1,2 1,2,2 1,3,2 1,4,2 1,5,2 1,6,2 1,7,2 1,1,3 1,2,3 1,3,3 1,4,3 1,5,3 1,6,3 1,7,3 1,1,4 1,2,4 1,3,4 1,4,4 1,5,4 1,6,4 1,7,4 2,1,1 ... M13 DS3, DS2, DS1 1,1,1 1,1,2 1,1,3 1,1,4 1,2,1 1,2,2 1,2,3 1,2,4 1,3,1 1,3,2 1,3,3 1,3,4 1,4,1 1,4,2 1,4,3 1,4,4 1,5,1 1,5,2 1,5,3 1,5,4 1,6,1 1,6,2 1,6,3 1,6,4 1,7,1 1,7,2 1,7,3 1,7,4 2,1,1 ... H-MVIP port index, DS1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 6,2 6,3 6,4 7,1 7,2 7,3 7,4 8,1 ...
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 14 Indexing for 2.048 Mbit/s Tributaries
SBI Bus SPE, LINK 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 2,1 ... Telecom Bus TUG-3, TUG-2, TU12 1,1,1 1,2,1 1,3,1 1,4,1 1,5,1 1,6,1 1,7,1 1,1,2 1,2,2 1,3,2 1,4,2 1,5,2 1,6,2 1,7,2 1,1,3 1,2,3 1,3,3 1,4,3 1,5,3 1,6,3 1,7,3 2,1,1 ... M13 DS3, DS2, E1 1,1,1 1,1,2 1,1,3 1,2,1 1,2,2 1,2,3 1,3,1 1,3,2 1,3,3 1,4,1 1,4,2 1,4,3 1,5,1 1,5,2 1,5,3 1,6,1 1,6,2 1,6,3 1,7,1 1,7,2 1,7,3 2,1,1 ... H-MVIP port index, E1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 8,1 ...
12.2 Clock and Frame Synchronization Constraints Depending on the modes of operation utilized, some coordination between LREFCLK, SREFCLK, LAC1, LDC1J1V1, SDC1FP and SAC1FP is required. Specifically, tighter constraints must be respected when supporting transparent virtual tributaries (TVTs) or 77.76 MHz buses. The following only applies when using the Telecom Bus. LREFCLK may be tied low when support is limited to DS3/E3 serial line interfaces. 12.2.1 SBI and Telecom Buses Both 19.44 MHz The rising and falling edges of LREFCLK must be aligned with a tolerance of +/10ns to the corresponding edges of SREFCLK. Restrictions on frame alignment pulses only exist when TVTs are supported. * The SAC1FP pulse must be 3n +/ 1 (where n = 0,1,2...) SREFCLK cycles before the LAC1 pulse.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
*
There is no restriction on the alignment of SDC1FP and LDC1J1V1.
12.2.2 SBI and Telecom Buses Both 77.76 MHz The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK. For reliable operation, the STM-1s used within the SBI and Telecom buses must be aligned in time. To this end, one may manipulate the LSTM[1:0] and SSTM[1:0] register bits and the position of the LAC1 and SDC1FP pulses. Table 15 summarizes the combinations. Table 15 77.76 SBI and Telecom Bus Alignment Options
Clock Cycles LAC1 leads SDC1FP (n = 0, 1 , 2...) LSTM[1:0] SSTM[1:0] 00 01 10 11 00 4n. 4n + 3 4n + 2 4n + 1 01 4n + 1 4n 4n + 3 4n + 2 10 4n + 2 4n + 1 4n 4n + 3 11 4n + 3 4n + 2 4n + 1 4n
As an alternate formulation, if SSTM[1:0] and LSTM[1:0] were converted to their decimal equivalents, one would have to satisfy the constraint: (LSTM - SSTM) mod 4 = (Clock Cycles LAC1 leads SDC1FP) mod 4
When TVTs are supported an additional constraint exists between SAC1FP and LAC1. Table 16 gives the permissible combinations. Table 16 TVT Constraints for 77.76MHz
Clock Cycles SAC1FP leads LAC1 (n = 0, 1 , 2...) LSTM[1:0] SSTM[1:0] 00 01 10 11 00 12n + 4 12n + 5 12n + 6 12n + 7 01 12n + 3 12n + 4 12n + 5 12n + 6 10 12n + 2 12n + 3 12n + 4 12n + 5 11 12n + 5 12n + 6 12n + 7 12n + 4
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
12.2.3 19.44 MHz SBI Bus and 77.76 MHz Telecom Bus The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK. For reliable operation, the STM-1s used within the Telecom bus must be aligned to the SREFCLK input. To this end, one may manipulate the LSTM[1:0] register bits and the position of the LAC1 pulses. Table 15 summarizes the combinations. Table 17 19.44 MHz SBI to 77.76 MHz Telecom to Bus Alignment Options
LSTM[1:0] LREFCLK Cycles LAC1 sampling edge leads SREFCLK rising edge 1 2 3 0
00 01 10 11
As alternate formulation, if LSTM[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint: (LSTM + 1) mod 4 = Clock Cycles LAC1 leads SREFCLK TVTs are not supported for this bus configuration. 12.2.4 77.76 MHz SBI Bus and 19.44 MHz Telecom Bus The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the rising edge of SREFCLK. For reliable operation, the STM-1s used within the SBI bus must be aligned to LREFCLK. To this end, one may manipulate the SSTM[1:0] register bits and the position of the SDC1FP pulses. Table 15 summarizes the combinations. Table 18 77.76 MHz SBI to 19.44 MHz Telecom to Bus Alignment Options
SSTM[1:0] SREFCLK Cycles SDC1FP sampling edge leads LREFCLK rising edge 1 2
00 01
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
10 11
3 0
As alternate formulation, if SSTM[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint: (SSTM + 1) mod 4 = Clock Cycles SDC1FP leads LREFCLK TVTs are not supported for this bus configuration. 12.3 SLCO96 The following is a comprehensive discussion of the roles and responsbilities of TEMUX-84 and external logic in the support of the SLCO96 standard, Bellcore TR-TSY-000008. While the TEMUX-84 handles most of the protocol functions, some external processing is required, especially of the datalink transported in the Fs bits. 12.3.1 Transmit While the TEMUX-84 supports transmission of AIS and the Yellow alarm, and supports signaling insertion, it is the responsibility of external logic to generate all F-bits. This means valid Ft and Fs bits as well as the datalink. To pass the F-bits transparently, the FDIS context bit must be set to logic 1 through the T1/E1 Transmitter Indirect Channel Data registers. The TEMUX-84 can insert robbed bit signaling. For the TEMUX-84 to insert the signaling into the correct frames (6th and 12th), it must know the multiframe alignment consistent with the encoding of the F-bits. Therefore, it is imperative a multiframe indication is provided by the system inteface. For the H-MVIP interface, this is effected by setting the CMMFP bit of the Master H-MVIP Interface Configuration register and asserting the CMVFPB input every 48 frames. The F-bit is encoded as per Table 42. For the SBI interface, the PPSSSSFR octets (those following V5) communicate multiframe alignment, signaling and the F-bits. The TRIB_TYP[1:0] bits of the EXSBI Tributary Control Indirect Access Data register should be set to "00" to configure the tributary to "Framed with CAS". Because the F-bits are being sourced from the system interface, controlled frame slips must be avoided, if the TX-ELST is being used, to maintain superframe integrity. The T1/E1 transmit clock must be referenced to CTCLK. For H-MVIP, CTCLK must be frequency locked to CMVFPB. For SBI, CTCLK must be frequency locked to SREFCLK. Two alternate configurations for SBI avoid the
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
need for the TX-ELST: the transmit clock is slaved to the data rate at the system interface or the TEMUX-84 acts as a timing master using the AJUST_REQ output to set the data rate. Insertion of nine state signaling is straight forward. A sixteen bit encoding (i.e. ABCD) is used regardless of whether the signaling is inserted from the system interface or via register access through the T1/E1 Transmit Per-Channel Controller. The ABCD state is sampled every 24 frames. The "AB" values are inserted into the first superframe and the "CD" values are inserted into the second. Thus, if toggling A or B bits are required, it is sufficient that A C or B D, respectively. 12.3.2 Receive The T1 framer will determine frame alignment within 13ms if it is programmed to frame to SLCO96 (i.e. ESF=0, FMS[1:0]=10) and is provided with valid SLCO96 frame overhead. The framer is tolerant to the existence of the data link. Once in frame, only the Ft bits are used to determine loss of frame and for monitoring framing bit errors. The presence of Yellow, Red, and AIS Carrier Fail Alarms is detected and integrated in accordance with the specifications defined in Bellcore TR-TSY000191. The datalink is not terminated within the TEMUX-84. Instead, it is provided on either the SBI or H-MVIP for external processing. Because the tributary may be subject to controlled frame slips, the external logic should be tolerant to the infrequent duplication or deletion of bits within the F-bit sequence. Signaling is terminated elegantly. The signaling for two consecutive superframes is captured as an aggregate presented as ABCD, with "CD" being the second set of A and B signaling bits. The ABCD bits are treated as cohesive state that is subject to debouncing (if enabled single bit errors will be filtered) and freezing. The four bits are available on the SBI Drop interface, the CASID[x] H-MVIP outputs and through the SIGX Indirect Channel Data Register registers. A C is an indication that the A bit is toggling. B D is an indication that the B bit is toggling. (Note, the following signaling states are all equivalent; they all represent toggling A and B bits: 0110, 1100, 0011, 1001.) An interrupt on change of signaling will only occur if the collected ABCD state changes, but not just from toggling A or B bits.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
12.4 DS3 Frame Format The TEMUX-84 provides support for both the C-bit parity and M23 DS3 framing formats. The DS3 frame format is shown in Figure 13. Figure 17 DS3 Frame Structure
84 bits M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 M-subframe 4 P 2 M-subframe 5 M1 M-subframe 6 M2 M-subframe 7 M3 F1 F1 F1 F1 F1 F1 F1 84 bits C1 C1 C1 C1 C1 C1 C1 84 bits F2 F2 F2 F2 F2 F2 F2 84 bits C2 C2 C2 C2 C2 C2 C2 84 bits F3 F3 F3 F3 F3 F3 F3 84 bits C3 C3 C3 C3 C3 C3 C3 84 bits F4 F4 F4 F4 F4 F4 F4 84 bits
Xx: X-Bit Channel Transmit: The TEMUX-84 inserts the FERF signal on the X-bits. FERF generation is controlled by either the FERF bit of the DS3 TRAN Configuration register or by detection of OOF, RED, LOS and AIS, as configured by the TEMUX-84 Master DS3 Alarm Enable register. Receive: The TEMUX-84 monitors the state and detects changes in the state of the FERF signal on the X-bits. Px: P-Bit Channel Transmit: The TEMUX-84 calculates the parity for the payload data over the previous M-frame and inserts it into the P1 and P2 bit positions. Receive: The TEMUX-84 calculates the parity for the received payload. Errors are accumulated in the DS3 PMON Parity Error Event Count registers. Mx: M-Frame Alignment Signal Transmit: The TEMUX-84 generates the M-frame alignment signal (M1 = 0, M2 = 1, M3 = 0). Receive: The TEMUX-84 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
consecutive M-frames while no discrepancies have occurred in the F-bits. M-bit errors are counted in the DS3 PMON Framing Bit Error Event Count registers. When one or more M-bit errors are detected in 3 out of 4 consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the DS3 Framer Configuration register is a logic 0). Fx: M-Subframe Alignment Signal Transmit: The TEMUX-84 generates the M-Subframe Alignment signal (F1=1, F2=0, F3=0, F4=1). Receive: The TEMUX-84 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. F-bit errors are counted in the DS3 PMON Framing Bit Error Event Count registers. An out-of frame defect is asserted if 3 F-bit errors out of 8 or 16 consecutive Fbits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration register). Cx: C-Bit Channels Transmit: When configured for M23 applications, the C-bits used for stuffing indication. When configured for C-bit parity applications, the C-bit Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The third Cbit in M-subframe 1 provides a far-end alarm and control (FEAC) signal. The FEAC channel is sourced by the DS3 XBOC block. The 3 C-bits in M-subframe 3 carry path parity information. The value of these 3 C-bits is the same as that of the P-bits. The 3 C-bits in M-subframe 4 are the FEBE bits. FEBE transmission is controlled by the DFEBE bit in the DS3 TRAN Diagnostic register and by the detection of receive framing bit and path parity errors. The 3 C-bits in Msubframe 5 contain the 28.2 kbit/s path maintenance datalink. These bits are inserted from the DS3 TDPR HDLC controller. The C-bits in M-subframes 2, 6, and 7 are unused and are set to logic 1. Receive: The CBITV register bit in the DS3 FRMR Status register is used to report the state of the C-bit parity ID bit, and hence whether a M23 or C-bit parity DS3 signal stream is being received. The FEAC channel on the third C-bit in Msubframe 1 is detected by the DS3 RBOC block. Path parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are reported in the DS3 PMON Path Parity Error Event Count and FEBE Event Count registers respectively. The path maintenance datalink signal is extracted by theDS3 RDLC HDLC receiver (if enabled).
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
12.5 Servicing Interrupts The TEMUX-84 will assert INTB to logic 0 when a condition which is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. Read the bits of the TEMUX-84 Master Interrupt Source register (0x0010) to identify which of the 14 interrupt registers (0x0011-0x001E) needs to be read to identify the interrupt. For example, a logic one read in the DS3E3INT register bit indicates that an interrupt identified in one of the three Master Interrupt Source DS3/E3 registers produced the interrupt. 2. Read the bits of the second level Master Interrupt Source register to identify the interrupt source. 3. Service the interrupt by reading the register containing the interrupt status bit that is asserted. 4. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB 12.6 Using the Performance Monitoring Features The counters in the DS3 PMON block has been sized as not to saturate if polled every second. The T1/E1 PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%). An accumulation interval is initiated by writing to one of the PMON event counter register addresses or by writing to the Global PMON Update register. After initiating an accumulation interval, 3.5 recovered clock periods (RCLK for the DS3 PMON) must be allowed to elapse to permit the PMON counter values to be properly transferred before the PMON registers may be read. The odds of any one of the T1/E1 counters saturating during a one second sampling interval go up as the bit error rate (BER) increases. At some point, the probability of counter saturation reaches 50%. This point varies, depending upon the framing format and the type of event being counted. The BER at which the probability of counter saturation reaches 50% is shown for various counters in Table 19 for E1 mode, and in Table 20 for T1 mode.
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Table 19 PMON Counter Saturation Limits (E1 mode) Counter FER CRCE FEBE BER 4.0 X 10-3 cannot saturate cannot saturate
Table 20 PMON Counter Saturation Limits (T1 mode) Counter FER Format SF ESF CRCE SF ESF BER 1.6 x 10-3 6.4 x 10-2 1.28 x 10-1 cannot saturate
Below these 50% points, the relationship between the BER and the counter event count (averaged over many one second samples) is essentially linear. Above the 50% point, the relationship between BER and the average counter event count is highly non-linear due to the likelihood of counter saturation. The following figures show this relationship for various counters and framing formats. These graphs can be used to determine the BER, given the average event count. In general, if the BER is above 10-3, the average counter event count cannot be used to determine the BER without considering the statistical effect of occasional counter saturation. Figure 18 illustrates the expected count values for a range of Bit Error Ratios in E1 mode.
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Figure 18 FER Count vs. BER (E1 mode)
9 Bit Error Rate (x 10 -3 ) 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 Framing Bit Error Count Per Second Average Count Over Many 1 Second Intervals
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-4 error is often due to more than one bit error. Thus, the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same explanation holds for the FEBE event counter. The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the following equation:
ae 8 ae oo c log c 1CRCE / / c e 8000 o/ c / 8*256 c / c / e o
Bit Error Rate = 1 - 10
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Figure 19 CRCE Count vs. BER (E1 mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 200 400 600 CRCE 800 1000 1200
Figure 20 illustrates the expected count values for a range of Bit Error Ratios in T1 mode. Figure 20 FER Count vs. BER (T1 ESF mode)
9
2 -
)
8 7 6 5 4 3 2 1 0 0
Average Count Over Many 1 Second Intervals
0 1 x ( e t a R r o r r E t i B
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At BERs below 10-4, there tends to be no more than one bit error per superframe, so the number of CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus, the relationship between BER and BEE count becomes nonlinear above a 10-4 BER. This must be taken into account when using ESF CRC6 counts to determine the BER.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the following equation:
ae 24 ae oo c log c 1BEE / / c e 8000 o/ c / 24*193 c / c / e o
Bit Error Rate = 1 - 10
Figure 21 CRCE Count vs. BER (T1 ESF mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 50 100 150 200 250 300 350 CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and should be ignored. Figure 22 CRCE Count vs. BER (T1 SF mode)
20
2 -
)
18 16 14 12 10 8 6 4 2 0 0 200 400
Average Count Over Many 1 Second Intervals
0 1 x ( e t a R r o r r E t i B
600
800
1000
1200
Bit Error Event Count Per Second
12.7 Using the Internal DS3 or E3 HDLC Transmitter It is important to note that access rate to the TDPR registers is limited by the rate of the internal DS3/E3 clock. Consecutive accesses to the TDPR Configuration,
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TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 1/8 that of the DS3 or E3 clock. This time is used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the TDPR registers. Upon reset of the TEMUX-84, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones Idle signal will be sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the one of the TEMUX-84 Master Interrupt Source registers, and the TEMUX-84 TDPR Interrupt Status registers to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register. Interrupt Driven Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set
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to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for a complete packet to be transmitted. Once data is available to be transmitted, then go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes of the packet have been written to the Transmit Data register, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Unless an error condition occurs, transmission will not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns. TDPR Interrupt Routine: Upon assertion of INTB, the source of the interrupt must first be identified by reading the TEMUX-84 Master Interrupt Source register (0020H) followed by reading one of the second level master interrupt source registers T1E1INT1, T1E1INT2, T1E1INT3, T1E1INT4 or DS3INT. Once the source of the interrupt has been identified as the TDPR in use, then the following procedure should be carried out: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear
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the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. 3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data. 5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted. If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level. Polling Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient
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warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: 1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6. 5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, then go to step 2. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 12.8 Using the Internal DS3 or E3 Data Link Receiver It is important to note that the access rate to the RDLC registers is limited by the rate of the internal DS3 or E3 clock. Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed at a rate no faster than 1/10 that of the selected RDLC high-speed system clock. This time is used by the highspeed system clock to sample the event and update the FIFO status. Instantaneous variations in the DS3 or E3 frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read RDLC registers. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit.
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After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC uses the TEMUX-84 INTB output and the TEMUX-84 Master Interrupt Source registers to determine when to read the RDLC Data register. In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the TEMUX-84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX-84 Master Interrupt Source register followed by one of the second level master interrupt source registers to identify one of the 3 HDLC receivers as the interrupt source. Once it has identified that the RDLC has generated the interrupt, it processes the data in the following order: 1. Read the RDLC Status register. The INTR bit should be logic 1.
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2.
If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. If COLS = 1, then set the EMPTY FIFO software flag. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. Read the RDLC Data register. Read the RDLC Status register. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. If COLS = 1, then set the EMPTY FIFO software flag. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will be delayed until the FIFO fill level is exceeded. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag. If PBS[2:0] = 1XX, discard the data byte read in step 5, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. If PBS[2:0] = 000, store the packet data.
3. 4.
5. 6. 7.
8. 9.
10.
11.
If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt.
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The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt. Figure 23 Typical Data Frame BIT: 8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
FLAG
Address (high) (low)
CONTROL
data bytes received and transferred to the FIFO Buffer
Frame Check Sequence 0 1 1 1 1 1 1 0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. Figure 24 Example Multi-Packet Operational Sequence
DATA INT FE LA FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 1 2 3 45 6 7
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F A D INT FE LA
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
Figure 24 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. The actual interrupt signal, INTB, is active low and will be the inverse of the INT signal shown in Figure 24. Also in this example, the programmable fill level set point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC Interrupt Control register. At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes active. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1. At points 2 and 6 the last byte of a packet is detected and interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO. At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared. 12.9 Using the Internal T1/E1 Data Link Receiver A time-sliced HDLC receiver processes the data links extracted from the tributaries. Receive packets are queued in a dedicated 128 byte FIFO for each
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tributary. The reading of the FIFOs by an external microprocessor is usually done in response to an interrupt, but polling is also supported. On power up of the system, the receiver defaults to a disabled state. One must use the RHDL Indirect Channel Data registers to program each tributary. The configuration of each tributary is independent of all others. The RHDL Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. The FIFO threshold is a global setting optimized for a particular system by trading off minimizing the number of interrupts against avoiding FIFO overflows. When the receiver is first enabled to delineate packets, it will assume the link is idle and immediately begin searching for flags. No bytes will be written into the FIFO until a flag is recognized. This is also true after an abort is detected. If packet delineation is disabled, all bytes are written raw into the FIFO. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The T1/E1 Receive HDLC processor (RHDL) can be used in a polled or interrupt driven mode for the transfer of packet data. In the polled mode, the processor controlling the RHDL must periodically read the RHDL Interrupt Status #1 register to determine if any tributaries need processing. In the interrupt driven mode, the processor controlling the RHDL uses the TEMUX-84 INTB output and the TEMUX-84 Master Interrupt Source registers to determine when to service the RHDL. In the case of interrupt driven data transfer from the RHDL to the processor, the INTB output of the TEMUX-84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX-84 Master Interrupt Source register followed by the Master Interrupt Source T1E1 register to determine if RHDL is the interrupt source. Once it has identified that the RHDL has generated the interrupt, it processes the data in the following order:
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1. Read the RHDL Interrupt Status #1 register. The value returned will indicate if any of RHDL Interrupt Status #2 through #11 should be read. Any bits returned as a logic 1 will indicate the associated tributary needs servicing. The bits in the RHDL Interrupt Status registers are write-one-to-clear, so the value read should be written back. Repeat steps 2 through 8 for each tributary with an INT bit set. 2. Write the RHDL Indirect Channel Address with the tributary index and set the FACCESS bit to logic 1. 3. Write the RHDL Indirect Status with 0x40 to initiate an indirect read. 4. Read RHDL Indirect Channel Data #2 register (0x011B) until CBUSY is returned as logic 0. Store the last FE, OVR, PKIN and PBS[2:0] bits read. 5. Read the HDLC data byte from the RHDL Indirect Channel Data #1 register (0x011A). 6. If OVR = 1, then discard the last frame and go to step 2. Overrun causes a reset of FIFO pointers and the loss of 128 bytes. Because an overflow likely occurred in the midst of a packet, discard all byte up to the next end-of-packet read. 7. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. If PBS[2:0] = 010, an abort has occur so discard the data byte read in step 5. If PBS[2:0] = 1XX, store the last byte of the packet and check the PBS[1:0] bits for CRC or non-integer-byte errors before deciding whether or not to keep the packet. If PBS[2:0] = 000, store the packet data. 8. If FE = 0, go to step 3 else service the next tributary or exit this interrupt service routine to wait for the next interrupt. If the RHDL data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
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12.10 Using the Internal T1/E1 Data Link Transmitter A time-sliced HDLC transmitter (THDL) formats the data links inserted into the T1/E1 tributaries. Raw packets are written by an external microprocessor to a dedicated 128 byte FIFO for each tributary. The HDLC transmitter reads the FIFO once a complete packet is written or when a specified FIFO fill threshold is passed. Also, Performance Reporting Messages (PRMs) may be transmitted autonomously once a second. The transmitter takes care of bit stuffing and insertion of the CRC protection and flags. By default, the HDLC transmitter operates in a clear channel mode in which the contents of the FIFO are transmitted verbatim without bit stuffing or CRC. If the FIFO becomes empty, flags will be transmitted. To enable the HDLC features, the DELIN context bit must be set via the THDL Indirect Channel Data registers. FIFO thresholds must be set to avoid overflows and underflows, which result in lost data and an abort sequence. The actual thresholds depend on operating system latencies and algorithms used to write the packets. The Upper Transmit Threshold value determines how many bytes must be written before transmission of an incomplete packet starts. It should be set at a value large enough to ensure an underflow does not occur before the complete packet is written under worst case conditions, such as excessive interrupt servicing. Note that complete packets are always transmitted regardless of the Upper Transmit Threshold value. A large Upper Transmit Threshold value may result in FIFO overflows if large packets are being written. To avoid overflows, it is recommended writes only resume after the Lower Interrupt Threshold is reached. The T1/E1 Transmit HDLC processor (THDL) can be used in a polled or interrupt driven mode for the transfer of packet data. In the polled mode, the processor controlling the THDL must periodically read the THDL Interrupt Status #1 register to determine if there's been a change in FIFO status. In the interrupt driven mode, the processor controlling the THDL uses the TEMUX-84 INTB output and the TEMUX-84 Master Interrupt Source registers to determine when to service the THDL. In the case of interrupt driven data transfer from the processor to THDL, the INTB output of the TEMUX-84 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TEMUX-84 Master Interrupt Source register followed by the Master Interrupt Source T1E1 register to determine if HDLC Transmitter is the interrupt source. Once it has identified that the THDL has generated the interrupt, it processes the data in the following order:
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1.
Read the THDL Interrupt Status #1 register. The value returned will indicate if any of THDL Interrupt Status #2 through #11 should be read. Any bits returned as a logic 1 will indicate the associated tributary needs servicing. The bits in the THDL Interrupt Status registers are write-one-to-clear, so the value read should be written back. Repeat steps 2 through 8 for each tributary with an INT bit set.
2. Write the THDL Indirect Channel Address with the tributary index and set the FACCESS bit to logic 1. 3. Write the THDL Indirect Status register (0x0130) with 0x40 to initiate an indirect read. 4. Read the THDL Indirect Status register until CBUSY is returned as logic 0. 5. Read the THDL Indirect Channel Data #2 register (0x0133). 6. A logic 1 OVRI indicates the FIFO for the tributary has overflowed and a packet has been corrupted. The entire contents of the current packet should be written again to the FIFO. 7. A logic 1 UDRI indicates the FIFO for the tributary has underrun, a packet has been corrupted and an abort has been sent. The entire contents of the current packet should be written again to the FIFO. 8. A logic 1 LFILLI indicates the FIFO level has dropped below a programmed threshold or has become empty. Packet data may be written. If EMPTY is logic 1, 128 bytes may be written. If EMPTY is logic 0, 128 minus the LINT[6:0] value bytes may be written. Write the THDL Indirect Status register (0x0130) with 0x00 to configure indirect writes. Also, the EOM bit should be initialized to zero and need not be written for each byte except the last of the packet. For each byte, repeat the following: a. Read the THDL Indirect Status register (0x0130) until CBUSY is returned as logic 0. b. If the byte is the last of a packet, write a logic 1 to the EOM bit position of the second THDL Indirect Channel Data Register (0x0134). c. Write a byte to the first THDL Indirect Channel Data Register (0x0133). This initiates the indirect write.
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12.11 Using the Time-Sliced T1/E1 Transceivers 12.11.1 Initialization
The configuration of the 84 T1/E1 framers is stored in context RAMs. These RAMs are initialized to all zeros upon release of reset. This effectively places the framers in T1 SF mode with frame slip buffers and jitter attenuators in both the ingress and egress paths. All trunk conditioning and alarm generation defaults to disabled. 12.12 T1 Automatic Performance Report Format Table 21 Performance Report Message Structure and contents
Octet No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 FLAG SAPI TEI CONTROL G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R G4 U1 U2 LB G1 R FCS FCS FLAG Bit 3 Bit 2 C/R Bit 1 EA EA G6 NI G6 NI G6 NI G6 NI
G3 FE G3 FE G3 FE G3 FE
LV SE LV SE LV SE LV SE
G5 G2 G5 G2 G5 G2 G5 G2
SL Nm SL Nm SL Nm SL Nm
Notes: 1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8).
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Table 22 Performance Report Message Structure Notes Octet No. 1 2 3 4 5,6 7,8 9,10 11,12 13,14 15 Octet Contents 01111110 00111000 00111010 00000001 00000011 Variable Variable Variable Variable Variable 01111110 Interpretation Opening LAPD Flag From CI: TEI=0,EA=1 Unacknowledged Frame Data for latest second (T') Data for Previous Second(T'-1) Data for earlier Second(T'-2) Data for earlier Second(T'-3) CRC16 Frame Check Sequence Closing LAPD flag SAPI=14, C/R=0, EA=0 From carrier: SAPI=14,C/R=1,EA=0
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Table 23 Performance Report Message Contents Bit Value G1=1 G2=1 G3=1 G4=1 G5=1 G6=1 SE=1 FE=1 LV=1 SL=1 LB=1 U1,U2=0 R=0 NmNI=00,01,10,11 Interpretation CRC ERROR EVENT =1 112.13 T1/E1 Framer Loopback Modes The TEMUX-84 provides two loopback modes for T1/E1 links to aid in network and system diagnostics. The internal T1/E1 line loopback can be initiated at any time via the P interface, but is usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the framer. T1/E1 Line Loopback T1/E1 Line loopback is initiated by setting the LLOOP bit to a 1 through the TJAT Indirect Channel Data register. When in line loopback mode, the appropriate T1/E1 framer in the TEMUX-84 is configured to internally connect the jitterattenuated clock and data from the RJAT to the transmit clock and data going to the M13 mux and SONET/SDH mapper. The RJAT must not be bypassed except
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for SONET/SDH byte synchronously mapped tributaries. Conceptually, the data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 25. Figure 25 T1/E1 Line Loopback
LIUs
M 13 M 13 D3MA M 13 M 13 DS3 TRAN M 13 M 13 M 13 M 13 M 13 PISO
Telecom Bus
M 13 M 13 VTPP TTOP TRAP
Line Loopback
INSBI (byte) TTM P (bit) T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRM R84 T1/E1 ELST84 T1/E1 SIGX84
Ingress H-M VIP EXSBI
H-M VIP
SBI 155
T1/E1 ELST84 INSBI Egress H-M VIP
M 13 M 13 VTPP
M 13 M 13 RTOP/ RTTB
RTDM (bit) EXSBI (byte)
Telecom Bus
M 13 M 13 D3MD M 13 M 13 DS3 FRM R M 13 M 13 M 13
H-M VIP
M 13 M13 SIPO
LIUs
T1/E1 Diagnostic Digital Loopback When Diagnostic Digital loopback is initiated, by writing a 1 to the DLOOP bit through the RJAT Indirect Channel Data register, the appropriate T1/E1 framer in the TEMUX-84 is configured to internally connect its transmit clock and data to the receive clock and data The data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 26.
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Figure 26 T1/E1 Diagnostic Digital Loopback
LIUs
M 13 M 13 D3MA M 13 M 13 DS3 TRAN M 13 M 13 M 13 M 13 M 13 PISO Ingress H-M VIP T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRM R84 T1/E1 ELST84 T1/E1 SIGX84 EXSBI
Telecom Bus
M 13 M 13 VTPP TTOP TRAP
INSBI (byte) TTM P (bit)
H-M VIP
SBI 155
T1/E1 ELST84 INSBI Egress H-M VIP
M 13 M 13 VTPP
M 13 M 13 RTOP/ RTTB
RTDM (bit) EXSBI (byte)
Telecom Bus
M 13 M 13 D3MD M 13 M 13 DS3 FRM R M 13 M 13 M 13
Diagnostic Loopback
H-M VIP
M 13 M13 SIPO
LIUs
12.14 DS3 and E3 Loopback Modes The TEMUX-84 provides two E3 and three DS3 M13 multiplexer loopback modes to aid in network and system diagnostics at the DS3 interface. The DS3 loopbacks can be initiated via the P interface whenever the DS3 framer/M13 multiplexer is enabled. The DS3 and E3 Master Data Source register controls the DS3 loopback modes. These loopbacks are also available when the DS3 mux is used with the DS3 mapper via the telecom bus interface. DS3 and E3 Diagnostic Loopback DS3 and E3 Diagnostic Loopback allows the transmitted DS3 or E3 stream to be looped back into the receive DS3 or E3 path, overriding the DS3 or E3 stream received on the RDAT/RPOS and RNEG/RLCV inputs. The RCLK signal is also substituted with the transmit DS3 or E3 clock, TCLK. While this mode is active, AIS may be substituted for the DS3 payload being transmitted on the TPOS/TDAT and TNEG/TMFP outputs. The configuration of the receive interface determines how the TNEG/TMFP signal is handled during loopback: if the UNI bit in the DS3 FRMR register is set, then the receive interface is configured for RDAT and RLCV, therefore the TNEG/TMFP signal is suppressed during loopback so that transmit MFP indications will not be seen nor accumulated as input LCVs. If the UNI bit is clear, then the interface is configured for bipolar signals RPOS and RNEG, therefore the TNEG is fed directly to the RNEG input. This diagnostic loopback can be used when the TEMUX-84 is configured as a
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multiplexer or as a framer only. The DS3/E3 loopback mode is shown diagrammatically in Figure 27. Figure 27 DS3/E3 Diagnostic Loopback Diagram
RCLK RPOS/ RDAT RNEG / RLCV
DS3/E3 FRMR
UNI TCLK TPOS/ TDAT TNEG/ TMFP Optional AIS Insertion
DS3/E3 TRAN
DS3 and E3 Line Loopback DS3 and E3 Line Loopbacks allow the received DS3/E3 streams to be looped back into the transmit DS3/E3 paths, overriding the DS3/E3 streams created internally by the framing unchannelized data or multiplexing of the lower speed tributaries. The transmit signals on TPOS/TDAT and TNEG/TMFP are substituted with the receive signals from RPOS/RDAT and RNEG/RLCV. The TCLK signal is also substituted with the receive DS3/E3 clock, RCLK. While this mode is active, AIS may be substituted for the DS3 payload being transmitted on the TPOS/TDAT and TNEG/TMFP outputs. Note that the transmit interface must be configured to be the same as the DS3/E3 FRMR receive interface for this mode to work properly. The DS3/E3 line loopback mode is shown diagrammatically in Figure 28. There is a second form of line loopback which only loops back the DS3/E3 payload. In this mode the DS3 framing overhead is regenerated for the received DS3/E3 stream and then retransmitted. Line loopback is selected with the LLOOP bit in the DS3 and E3 Master Data Source register and payload loopback is selected by the PLOOP bit in the same register.
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Figure 28 DS3 and E3 Line Loopback Diagram
RCLK RPOS / RDAT RNEG / RLCV
DS3/E3 FRMR
TCLK TPOS / TDAT TNE G/ TMFP
DS3/E3 TRAN
DS2 Demultiplex Loopback DS2 Demultiplex Loopbacks allow each of the seven demultiplexed DS2 streams to be looped back into the MX23 and multiplexed up into the transmit DS3 stream. This overrides the tributary DS2 streams coming from the MX12s. The DS2 loopback mode is shown diagrammatically in Figure 29 and is enabled via the MX23 Loopback Activate register. Figure 29 DS2 Loopback Diagram
RCLK RPOS/ RDAT RNEG/ RLCV
DS3 FRMR MX23
Optional DEMUX AIS Insertion
DS2 Tributary Loopback path TCLK TPOS/ TDAT TNEG/ TMFP
DS3 TRAN
F MX12 #7 F R MX12 #6 RM FR MX12 #5 M R F MR MX12 #4 R F MR MX12 #3 RR F M MX12 #2 RR F MX12 #1 RM MR R
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12.15 Telecom Bus Mapper/Demapper Loopback Modes The TEMUX-84 provides two loopbacks at the telecom bus interface to aid in network and system diagnostics at the SONET/SDH interface. These loopback modes can be enabled via the microprocessor whenever the SONET/SDH block is enabled as the mapper for the T1/E1 framer slices or as the mapper for the DS3 framer or M13 Multiplexer. Telecom Diagnostic Loopback The Telecom Bus Diagnostic Loopback allows the transmitted telecom bus stream to be looped back into the receive SONET/SDH receive path, overriding the data stream received on the telecom drop bus inputs. While Telecom diagnostic loopback is active, valid SONET/SDH data continues to be transmitted on the telecom add bus outputs. The entire telecom drop bus is overwritten by the diagnostic loopback even though only one STS-1 SPE, STM-1/VC4 TUG3 or STM-1/VC3 is generated by the egress VTPP onto the telecom add bus. This loopback is only available for VT1.5/VT2/TU11/TU12 mapped tributaries. DS3 mapped tributaries must use the DS3 diagnostic loopback. The telecom bus diagnostic loopback mode is shown diagrammatically in Figure 30. Figure 30 Telecom Diagnostic Loopback Diagram
LDDATA[7:0] LDDP LDPL LDC1J1
VTPP VT/TU Payload Processor
RTOP Receive Tributary Path O/H
LADATA[7:0] LADP LAPL LAC1J1V1 LAC1
VTPP VT/TU Payload Processor
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Telecom Line Loopback The Telecom Bus Line Loopback allows the received telecom drop bus data to be looped back out the telecom add bus after being processed by both the ingress and egress VTPPs. Both VTPP must be setup for the same STS-1 SPE, STM1/VC4 TUG3 or STM-1/VC3 otherwise no loopback data will get through. The ingress data path is not affected by the telecom line loopback. This loopback is only available for VT1.5/VT2/TU11/TU12 mapped tributaries. DS3 mapped tributaries must use the DS3 line loopback. The Telecom bus line loopback mode is shown diagrammatically in Figure 31. Figure 31 Telecom Line Loopback Diagram
LDDATA[7:0] LDDP LDPL LDC1J1
VTPP VT/TU Payload Processor
RTOP Receive Tributary Path O/H
LADATA[7:0] LADP LAPL LAC1J1V1 LAC1
VTPP VT/TU Payload Processor
TTOP Transmit Tributary Path O/H
12.16 SBI Bus Data Formats The TEMUX-84 uses the Scaleable Bandwidth Interconnect (SBI) bus as a high density link interconnect with devices processing T1s, E1s, DS3s, E3s, transparent virtual tributaries and arbitary bandwidth payloads. The SBI bus is a multi-point to multi-point bus capable of interconnecting up to four TEMUX-84 devices in parallel (if connected to a 77.76 MHz bus) with other link layer or tributary processing devices. Multiplexing Structure The SBI structure uses a locked SONET/SDH structure fixing the position of the TU-3 relative to the STS-3/STM-1. The SBI is also of fixed frequency and
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alignment as determined by the reference clock (SREFCLK) and frame indicator signals (SAC1FP and SDC1FP). Frequency deviations are compensated by adjusting the location of the T1/E1/DS3/TVT1.5/TVT2 channels using floating tributaries as determined by the V5 indicator and payload signals (SDV5, SAV5, SDPL and SAPL). TVTs also allow for synchronous operation where SONET/SDH tributary pointers are carried within the SBI structure in place of the V5 indicator and payload signals (SDV5, SAV5, SDPL and SAPL). Table 24 shows the bus structure for carrying T1, E1, TVT1.5, TVT2, DS3 and E3 tributaries in a SDH STM-1 like format. Up to 84 T1s, 63 E1s, 84 TVT1.5s, 63 TVT2s, 3 DS3s or 3 E3s are carried within the octets labeled SPE1, SPE2 and SPE3 in columns 16-270. All other octets are unused and are of fixed position. The frame signal (SAC1FP or SDC1FP) occurs during the octet labeled C1 in Row 1 column 7. The Add and Drop buses have independent frame signals to allow for arbitrary alignment of the two buses. Table 24 represents a 19.44 Mbit/s signal. The structure is presented on a 77.76 MHz bus by byte interleaving it with three other like structures. The multiplexed links are separated into three Synchronous Payload Envelopes called SPE1, SPE2 and SPE3. Each envelope carries up to 28 T1s, 21 E1, 28 TVT1.5s, 21 TVT2s, a DS3 or an E3. SPE1 carries the T1s numbered 1,1 through 1,28, E1s numbered 1,1 through 1,21, DS3 number 1,1 or E3 number 1,1. SPE2 carries T1s numbered 2,1 through 2,28, E1s numbered 2,1 through 2,21, DS3 number 2,1 or E3 number 2,1. SPE3 carries T1s numbered 3,1 through 3,28, E1s numbered 3,1 through 3,21, DS3 number 3,1 or E3 number 3,1. TVT1.5s are numbered the same as T1 tributaries and TVT2s are numbered the same as E1 tributaries.
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Table 24 Structure for Carrying Multiplexed Links
SBI Column 1 Row 1 2 6 7 8 15 16 17 18 19 268 269 270
- *** - C1 - *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2 SPE3 - *** - *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2 SPE3
9
1
2
3
3
- SPE1SPE2SPE3SPE1 5 6 6 6 7
SPE1SPE2 SPE3 90 90 90
SPE Column
The TEMUX-84 when enabled for SBI interconnection will add and drop either 28 T1s, 21 E1s, a DS3 or an E3 into each of the three Synchronous Payload Envelopes, SPE1, SPE2 or SPE3. Each SPE is independent of the others. When T1 or E1 tributaries are sourced from the telecom bus via VT1.5, TU11, VT2 or TU12 mappings, the TEMUX-84 also supports a mix of transparent virtual tributaries with T1s and E1s. A restriction to this are that only VT1.5s, TU11s and T1s can be mixed together or VT2s, TU12s and E1s can be mixed together. Another restriction is that the telecom bus and SBI bus must run from the same clock with a fixed framing offset, ie. SREFCLK and LREFCLK are externally connected. Tributary Numbering Tributary numbering for T1 and E1 uses the SPE number, followed by the Tributary number within that SPE and are numbered sequentially. Table 25 and Table 26 show the T1 and E1 column numbering and relates the tributary number to the SPE column numbers and overall SBI column structure. Numbering for DS3 or E3 follows the same naming convention even though there is only one DS3 or E3 per SPE. TVT1.5s and TVT2s follow the same numbering conventions as T1 and E1 tributaries respectively. SBI columns 16-18 are unused for T1, E1, TVT1.5 and TVT2 tributaries. Table 25 T1/TVT1.5 Tributary Column Numbering T1#
1,1 2,1 3,1 1,2 8,36,64
SPE1 Column SPE2 Column SPE3 Column
7,35,63 7,35,63 7,35,63
SBI Column
19,103,187 20,104,188 21,105,189 22,106,190
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
2,2
***
8,36,64 34,62,90 34,62,90 34,62,90
23,107,191 100,184,268 101,185,269 102,186,270
1,28 2,28 3,28
Table 26 E1/TVT2 Tributary Column Numbering E1#
1,1 2,1 3,1 1,2 2,2
***
SPE1 Column SPE2 Column SPE3 Column
7,28,49,70 7,28,49,70 7,28,49,70 8,29,50,71 8,29,50,71 27,48,69,90 27,48,69,90 27,48,69,90
SBI Column
19,82,145,208 20,83,146,209 21,84,147,210 22,85,148,211 23,86,149,212 79,142,205,268 80,143,206,269 81,144,207,270
1,21 2,21 3,21
SBI Timing Master Modes The TEMUX-84 supports both synchronous and asynchronous SBI timing modes. Synchronous modes apply only to T1 and E1 tributaries and are used with ingress elastic stores to rate adapt the receive tributaries to the fixed SBI data rate. Asynchronous modes allow T1, E1, DS3 and transparent tributaries to float within the SBI structure to accommodate differences in timing. In synchronous SBI mode, the T1 DS0s and E1 timeslots are in a fixed format and do not move relative to the SBI structure. The SBI frame pulse, SAC1FP or SDC1FP, in synchronous mode can be enabled to indicate CAS signaling multiframe alignment by pulsing once every 12th 2KHz frame pulse period. SREFCLK sets the ingress rate from the receive elastic store. In Asynchronous modes, timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures within the SBI. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet for DS3 and E3 mappings). When the source is slower than the SBI the floating payload is retarded by leaving the octet after the V3 or
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
H3 octet unused. Both these rate adjustments are indicated by the SBI control signals. Transparent VTs can float in the SBI structure in two ways. The first method uses valid V1 and V2 pointers to indicate positive and negative pointer justifications. The second methods uses the SBI signals SDV5, SAV5, SDPL and SAPL to indicate rate adjustments. In the DROP bus, the TEMUX-84 will always provide both valid pointers with valid SDV5 and SDPL signals. On the SBI Add Bus, the TEMUX-84 needs to be configured on a per tributary basis for either transparent VT mode. Transparent VT operation is configured on a per tributary basis via the ETVT and ETVTPTRDIS bits in the TTMP Tributary control registers. On the DROP BUS the TEMUX-84 is timing master as determined by the arrival rate of data over the SBI. On the ADD BUS the TEMUX-84 can be either the timing master or the timing slave. When the TEMUX-84 is the timing slave it receives its transmit timing information from the arrival rate of data across the SBI ADD bus. When the TEMUX-84 is the timing master it signals devices on the SBI ADD bus to speed up or slow down with the justification request signal, SAJUST_REQ. The TEMUX-84 as timing master indicates a speedup request to a Link Layer SBI device by asserting the justification request signal high during the V3 or H3 octet. When this is detected by the Link Layer it will speed up the channel by inserting extra data in the next V3 or H3 octet. The TEMUX-84 indicates a slow down request to the Link Layer by asserting the justification request signal high during the octet after the V3 or H3 octet. When detected by the Link Layer it will retard the channel by leaving the octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request. Arbitrary Bandwidth Support Data streams of an arbitrary bit rate up to the capacitry of an SPE may be transported across the SPEs to and from the Flexible Bandwidth Ports. When one (or more) of the SBI is programmed to support this, the SAPL and SDPL signals may be asserted and deasserted at arbitrary times to allow precise control of the payload bit rate. On the DROP Bus, data received on the FBWDAT[3:1] signals are collected into complete bytes and are presented on SDDATA[7:0] with SDPL asserted high. No flow control is implemented on the DROP bus. On the ADD Bus, the EFWBDREQ[3:1] signals request data at a specific rate. The data is read from a shallow FIFO. To keep the FIFO half full, the
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
SAJUST_REQ output is asserted to fetch data across the ADD bus. In turn, the data source responds with data and the SAPL signal asserted an equal or less number of cycles than SAJUST_REQ is asserted. Significant latency is tolerated. Note that the some applications require an exact one-to-one correspondence between SAJUST_REQ and data bytes. SBI Link Rate Information The TEMUX-84 SBI bus provides a method for carrying link rate information between devices. Two methods are specified, one for T1 and E1 channels and the second for DS3 and E3 channels. For T1 and E1, the link rate information is always generated on the Drop bus and always ignored on the Add bus. For DS3 and E3, only the ClkRate field of the link rate byte is valid on the Drop bus and the use is optional on the Add bus as specified by the CLK_MODE[1:0] bits of the EXSBI Tributary Control Indirect Access Data register. Link rate information is not available for TVTs. These methods use the reference 19.44 MHz SBI clock and the SAC1FP frame synchronization signal to measure channel clock ticks and clock phase for transport across the bus. The T1 and E1 method allows for a count of the number of T1 or E1 rising clock edges between 2 KHz SDC1FP frame pulses. This count is encoded in ClkRate[1:0] to indicate that the nominal number of clocks, one more than nominal or one less than nominal should be generated during the SDC1FP period. This method also counts the number of 19.44 MHz clock rising edges after sampling SDC1FP high to the next rising edge of the T1 or E1 clock, giving the ability to control the phase of the generated clock. The link rate information passed across the SBI bus via the V4 octet and is shown in Table 27. Table 28 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet. Note that while the TEMUX-84 generates valid link rate information on the SBI Drop bus, it ignores the V4 byte on the Add bus.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 27 SBI T1/E1 Link Rate Information SDC1FP SREFCLK T1/E1 CLK Link Rate Octet T1/E1 Format Bit # 7 ALM *** *** ***
Clock Count
a 5:4
Phase 3:0 Phase[3:0]
a
6 0
ClkRate[1:0]
Table 28 SBI T1/E1 Clock Rate Encoding ClkRate[1:0] "00" - Nominal "01" - Fast "1x" - Slow T1 Clocks / 2KHz 772 773 771 E1 Clocks / 2 KHz 1024 1025 1023
The method for transferring DS3 link rate information across the SBI passes the encoded count of DS3 clocks between 2KHz SAC1FP/SDC1FP pulses in the same method used for T1/E1 tributaries, but does not pass any phase information. The other difference from T1/E1 link rate is that ClkRate[1:0] indicates whether the nominal number of clocks are generated or if four fewer or four extra clocks are generated during the SAC1FP/SDC1FP period. The format of the DS3 link rate octet is shown in Table 29. This is passed across the SBI via the Linkrate octet which follows the H3 octet in the column, see Table 35. Table 30 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 29 DS3 Link Rate Information Link Rate Octet DS3 Format Bit # 7 ALM 6 0 5:4 ClkRate[1:0] 3:0 Unused
Table 30 DS3 Clock Rate Encoding ClkRate[1:0] "00" - Nominal "01" - Fast "1x" - Slow SBI Alarms The TEMUX-84 transfers alarm conditions across the SBI for T1, E1 and DS3 tributaries but not valid for transparent VTs. Table 27 and Table 29 show the alarm indication bit, ALM, as bit 7 of the Link Rate Octet. Devices connecting to the TEMUX-84 which do not support alarm indications must set this bit to 0 on the SBI ADD bus. The presence of an alarm condition is indicated by the ALM bit set high in the Link Rate Octet. For T1 and E1 tributaries, either an out-of-frame condition or Red alarm (persistent out-of-frame) may set the ALM as determined by the IREDEN and IOOFEN per-tributary configuration bits. The absence of an alarm condition is indicated by the ALM bit set low in the Link Rate Octet. In the egress direction the TEMUX-84 can be configured to use the alarm bit to force AIS on a per link basis by the EALMEN or EGRALMEN register bits. T1 Tributary Mapping Table 31 shows the format for mapping 84 T1s within the SPE octets. The DS0s and framing bits within each T1 are easily located within this mapping for channelized T1 applications. It is acceptable for the framing bit to not carry a valid framing bit on the Add Bus since the physical layer device will provide this information. Unframed T1s use the exact same format for mapping 84 T1s into the SBI except that the T1 tributaries need not align with the frame bit and DS0 locations. The V1,V2 and V4 octets are not used to carry T1 data and are either reserved or used for control across the interface. When enabled, the V4 octet is DS3 Clocks / 2KHz 22368 22372 22364
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the Link Rate octet of Table 27. It carries alarm and clock phase information across the SBI bus. The V1 and V2 octets are unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not carry any information and are fixed to a zero value. The V3 octet carries a T1 data octet but only during rate adjustments as indicated by the V5 indicator signals, DV5 and AV5, and payload signals, SDPL and SAPL. The PPSSSSFR octets carry channel associated signaling (CAS) bits and the T1 framing overhead. The DS0 octets are the 24 DS0 channels making up the T1 link. The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded for T1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2KHz multi-frame. The position of the floating T1 is identified via the V5 Indicator signals, SDV5 and SAV5, which locate the V5 octet. When the T1 tributary rate is faster than the SBI nominal T1 tributary rate, the T1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the V3 location. When the T1 tributary rate is slower than the nominal SBI tributary rate the T1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet that was originally in that position. Table 31 T1 Framing Format
COL # ROW # 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 1-18 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused T1#1,1 19 V1 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V2 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V3 DS0#1 T1#2,1-3,28 20-102 V1 V2 V3 T1#1,1 103 V5 DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 T1#2,1-3,28 104-186 T1#1,1 187 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 PPSSSSFR DS0#3 T1#2,1-3,28 188-270 -
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V4 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22
V4 -
DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23
-
DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24
-
The P1P0S1S2S3S4FR octet carries T1 framing in the F bit and channel associated signaling in the P1P0and S1S2S3S4bits. Channel associated signaling is optional. The R bit is reserved and is set to 0. The P1P0bits are used to indicate the phase of the channel associated signaling and the S1S2S3S4 bits are the channel associated signaling bits for the 24 DS0 channels in the T1. Table 32 shows the channel associated signaling bit mapping and how the phase bits locate the sixteen state CAS mapping for super frame and extended superframe formats. When using four state CAS then the signaling bits are A1-A24, B1-B24, A1-A24, B1-B24 in place of are A1-A24, B1-B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24 signaling bits. When the SYNCH_TRIB bit is set for a tributary, the DS0 alignment is precisely as presented in Table 31, and the P1P0 and S1S2S3S4bits in the first row of Table 32 are aligned to the multiframe indicated by the SDC1FP signal, be it an input or output. The F-bit positions in Table 32 have an arbitrary alignment relative to the P1P0 bits that will change with each controlled frame slip; that illustrated is only an example. The signaling contained within the robbed bit positions of the DS0s will also have an arbitrary alignment relative to the P1P0 bits. Table 32 T1 Channel Associated Signaling bits
SF S1 A1 A5 A9 A13 S2 A2 A6 A10 A14 S3 A3 A7 A11 A15 S4 A4 A8 A12 A16 F F1 S1 F2 S2 ESF F M1 C1 M2 F1 P1 P0 00 00 00 00
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
A17 A21 B1 B5 B9 B13 B17 B21 C1 C5 C9 C13 C17 C21 D1 D5 D9 D13 D17 D21
A18 A22 B2 B6 B10 B14 B18 B22 C2 C6 C10 C14 C18 C22 D2 D6 D10 D14 D18 D22
A19 A23 B3 B7 B11 B15 B19 B23 C3 C7 C11 C15 C19 C23 D3 D7 D11 D15 D19 D23
A20 A24 B4 B8 B12 B16 B20 B24 C4 C8 C12 C16 C20 C24 D4 D8 D12 D16 D20 D24
F3 S3 F4 S4 F5 S5 F6 S6 F1 S1 F2 S2 F3 S3 F4 S4 F5 S5 F6 S6
M3 C2 M4 F2 M5 C3 M6 F3 M7 C4 M8 F4 M9 C5 M10 F5 M11 C6 M12 F6
00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11
T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary link rate adjustments are optionally passed across the SBI via the V4. T1 tributary alarm conditions are optionally passed across the SBI bus via the link rate octet in the V4 location. In synchronous mode the T1 tributary mapping is fixed to that shown in Table 31 and rate justifications are not possible using the V3 octet. The clock rate information within the link rate octet in the V4 location is not used in synchronous mode. E1 Tributary Mapping Table 33 shows the format for mapping 63 E1s within the SPE octets. The timeslots and framing bits within each E1 are easily located within this mapping for channelized E1 applications. It is acceptable for the framing bits to not carry valid framing information on the Add Bus since the physical layer device will provide this information. Unframed E1s use the exact same format for mapping 63 E1s into the SBI except that the E1 tributaries need not align with the timeslot locations associated with channelized E1 applications. The V1,V2 and V4 octets are not used to carry E1 data and are either reserved or used for control information across the interface. When enabled, the V4 octet carries clock phase information across the SBI. The V1 and V2 octets are unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not carry any
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information and are fixed to a zero value. The V3 octet carries an E1 data octet but only during rate adjustments as indicated by the V5 indicator signals, SDV5 and SAV5, and payload signals, SDPL and SAPL. The PP octets carry channel associated signaling phase information and E1 multiframe alignment. TS#0 through TS#31 make up the E1 channel. The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded for E1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2KHz multi-frame. The position of the floating E1 is identified via the V5 Indicator signals, SDV5 and SAV5, which locate the V5 octet. When the E1 tributary rate is faster than the E1 tributary nominal rate, the E1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the V3 location. When the E1 tributary rate is slower than the nominal rate the E1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet that was originally in that position. When the SYNCH_TRIB bit is set for a tributary, the timeslot alignment is precisely as presented in Table 33. Table 33 E1 Framing Format
COL # ROW # 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 1-18 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 19 V1 TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29 V2 TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29 V3 TS#1 20-81 V1 V2 V3 82 V5 TS#2 TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30 R TS#2 TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30 R TS#2 83-144 145 PP TS#3 TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31 PP TS#3 TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31 PP TS#3 146-207 208 TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R TS#0 TS#4 209-270 -
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29 V4 TS#1 TS#5 TS#9 TS#13 TS#17 TS#21 TS#25 TS#29
V4 -
TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30 R TS#2 TS#6 TS#10 TS#14 TS#18 TS#22 TS#26 TS#30
-
TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31 PP TS#3 TS#7 TS#11 TS#15 TS#19 TS#23 TS#27 TS#31
-
TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R TS#0 TS#4 TS#8 TS#12 TS#16 TS#20 TS#24 TS#28 R
-
When using channel associated signaling (CAS) TS#16 carries the ABCD signaling bits and the timeslots 17 through 31 are renumbered 16 through 30. The PP octet is 0h for all frames except for the frame which carries the CAS for timeslots 15/30 at which time the PP octet is C0h. The first octet of the CAS multi-frame, RRRRRRRR, is reserved and should be ignored by the receiver when CAS signaling is enabled. Table 34 shows the format of timeslot 16 when carrying channel associated signaling. Table 34 E1 Channel Associated Signaling bits
TS#16[0:3] RRRR ABCD1 ABCD2 ABCD3 ABCD4 ABCD5 ABCD6 ABCD7 ABCD8 ABCD9 ABCD10 ABCD11 ABCD12 ABCD13 ABCD14 ABCD15 TS#16[4:7] RRRR ABCD16 ABCD17 ABCD18 ABCD19 ABCD20 ABCD21 ABCD22 ABCD23 ABCD24 ABCD25 ABCD26 ABCD27 ABCD28 ABCD29 ABCD30 PP 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0
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E1 tributary asynchronous timing is compensated via the V3 octet. E1 tributary link rate adjustments are optionally passed across the SBI via the V4 octet. E1 tributary alarm conditions are optionally passed across the SBI bus via the link rate octet in the V4 location. In synchronous mode the E1 tributary mapping is fixed to that shown in Table 33 and rate justifications are not possible using the V3 octet. The clock rate information within the link rate octet in the V4 location is not used in synchronous mode. DS3 Tributary Mapping Table 35 shows a DS3 tributary mapped within the first synchronous payload envelope SPE1. The V5 indicator pulse identifies the V5 octet. The DS3 framing format does not follow an 8KHz frame period so the floating DS3 multi-frame located by the V5 indicator, shown in heavy border grey region in Table 35, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will often be asserted twice per H1 frame, as is shown by the second V5 octet in Table 35. The V5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet. Table 35 DS3 Framing Format
SPE COL # SBI COL# ROW 1 2 3 4 5 6 7 8 9 1,4,7,10 Unused Unused Unused Unused Unused Unused Unused Unused 13 H1 H2 H3 Unused Unused Unused Unused Unused 16 V5 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 *** DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 184 DS3 DS3 DS3 DS3 DS3 DS3 DS3 V5 DS3 *** DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 268 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 1 DS3 2-56 DS3 57 DS3 58-84 DS3 Col 85
Unused Linkrate
Because the DS3 tributary rate is less than the rate of the grey region, padding octets are interleaved with the DS3 tributary to make up the difference in rate. Interleaved with every DS3 multi-frame are 35 stuff octets, one of which is the V5 octet. These 35 stuff octets are spread evenly across seven DS3 subframes. Each DS3 subframe is eight blocks of 85 bits. The 85 bits making up a DS3 block are padded out to be 11 octets. Table 36 shows the DS3 block 11 octet format
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where R indicates a stuff bit, F indicates a DS3 framing bit and I indicates DS3 information bits. Table 37 shows the DS3 multi-frame format that is packed into the grey region of Table 35. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet and B indicates the 11 octet DS3 block. Each row in Table 37 is a DS3 multi-frame. The DS3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after the V5 octet is added every sixth frame. Table 36 DS3 Block Format
Octet # Data 1 2 3 4 5 6 7 8 9 10 11
RRRFIIII
8*I
8*I
8*I
8*I
8*I
8*I
8*I
8*I
8*I
8*I
Table 37 DS3 Multi-frame Stuffing Format
V5 V5 V5 V5 V5 V5 4*R 4*R 4*R 4*R 4*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B
DS3 asynchronous timing is compensated via the H3 octet. DS3 link rate adjustments are optionally passed across the SBI via the Linkrate octet. DS3 alarm conditions are optionally passed across the SBI bus via the Linkrate octet. E3 Tributary Mapping Table 38 shows a E3 tributary mapped within the first synchronous payload envelope SPE1. The V5 indicator pulse identifies the V5 octet. The E3 framing format does not follow an 8KHz frame period so the floating frame located by the V5 indicator and shown in grey in Table 38, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will be asserted two or three times per H1 frame, as is shown by the second and third V5 octet in Table 38. The V5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet.
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Table 38 E3 Framing Format
SPE COL # SBI COL# ROW 1 2 3 4 5 6 7 8 9 1,4,7,10 Unused Unused Unused 13 H1 H2 H3 16 V5 E3 E3 E3 E3 E3 E3 E3 E3 *** E3 E3 E3 E3 E3 E3 E3 E3 E3 70 E3 E3 E3 V5 E3 E3 E3 E3 E3 *** E3 E3 E3 E3 E3 E3 E3 E3 E3 130 E3 E3 E3 E3 E3 E3 V5 E3 E3 *** E3 E3 E3 E3 E3 E3 E3 E3 E3 268 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 1 E3 2-18 E3 19 E3 20-38 E3 39 E3 40-84 E3 85
Unused Linkrate Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
When carrying framed E3, only the ITU-T Rec. G.751 format is supported. Unframed E3 is carried clear channel. Because the E3 tributary rate is less than the rate of the gray region, padding octets are interleaved with the E3 tributary to make up the difference in rate. Interleaved with every E3 frame is an alternating pattern of 81 and 82 stuff octets, one of which is the V5 octet. These 81 or 82 stuff octets are spread evenly across the E3 frame. Each E3 subframe is 48 octet which is further broken into 4 equal blocks of 12 octets each. Table 39 shows the alternating E3 frame stuffing format that is packed into the gray region of Table 38. Note that there are 6 stuff octets after the V5 octet in one frame and 5 stuff octets after the V5 octet in the next frame. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet, D indicates an E3 data octet, FAS indicates the first byte of the 10 bit E3 Frame Alignment Signal.
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Table 39 E3 Frame Stuffing Format
V5 6*R 5*R 5*R 5*R V5 5*R 5*R 5*R 5*R FAS 11*D 5*R 5*R 5*R 5*R 5*R 5*R 5*R 5*R 12*D 12*D 12*D 12*D 12*D 12*D 12*D 12*D 5*R 5*R 5*R 5*R 5*R 5*R 5*R 5*R 12*D 12*D 12*D 12*D 12*D 12*D 12*D 12*D 5*R 5*R 5*R 5*R 5*R 5*R 5*R 5*R 12*D 12*D 12*D 12*D 12*D 12*D 12*D 12*D
12*D 12*D 12*D FAS 11*D
12*D 12*D 12*D
E3 asynchronous timing is compensated via the H3 octet. E3 link rate adjustments are optionally passed across the SBI via the Linkrate octet. E3 alarm conditions are optionally passed across the SBI bus via the Linkrate octet. Flexible Bandwidth Mapping When the OPMODE_SPEx[2:0] register bits for an SPE are binary 100, the SBI is configured to transport an arbitrary bandwidth up to the capacity of an SPE. In this mode the SDPL and SAPL signals identify individual valid bytes. For each SPE, every third byte in columns 16 through 270, inclusive, has the potential for presenting data. Be aware that although columns 13 though 15 carry no payload, the byte positions for rows 1 through 4 are driven by the Drop bus with SDPL unconditionally low. Transparent VT1.5/TU11 Mapping VT1.5 and TU11 virtual tributaries, TVT1.5s, are transported across the SBI bus in a similar manner to the T1 tributary mapping. Table 40 shows the transparent structure where "I" is used to indicate information bytes. There are two options when carrying virtual tributaries on the SBI bus, the primary difference being how the floating V5 payload is located. The first option is locked TVT mode which carries the entire VT1.5/TU11 virtual tributary indicated by the shaded region in Table 40. Locked is used to indicate that the location of the V1,V2 pointer is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5 payload. In this mode the V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, may be generated but must be ignored by the receiving device. In locked mode timing is always sourced by the
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transmitting side, therefore justification requests are not used and the SAJUST_REQ signal is ignored. Other than the V1 and V2 octets which must carry valid pointers, all octets can carry data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 40. The second option is floating TVT mode which carries the payload comprised of the V5 and I octets within the shaded region of Table 40. In this mode the V1,V2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. The V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, must be valid and are used to locate the floating payload. The justification request signal can be used to control the timing on the add bus. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 40. The TEMUX-84 supports both TVT modes simultaneously in the SBI DROP bus and is configurable on a per tributary basis in the SBI ADD bus. Table 40 Transparent VT1.5/TU11 Format
COL # ROW # 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 1-18 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused VT1.5#1,1 19 V1 I I I I I I I I V2 I I I I I I I I V3 I I I #2,1-3,28 20-102 V1 V2 V3 VT1.5#1,1 103 V5 I I I I I I I I I I I I I I I I I I I I I #2,1-3,28 104-186 VT1.5#1,1 187 I I I I I I I I I I I I I I I I I I I I I I #2,1-3,28 188-270 -
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5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
I I I I I V4 I I I I I I I I
V4 -
I I I I I I I I I I I I I I
-
I I I I I I I I I I I I I I
-
Transparent VT2/TU12 Mapping VT2 and TU12 virtual tributaries, TVT2s, are transported across the SBI bus in a similar manner to the E1 tributary mapping. The TEMUX-84 supports both TVT modes simultaneously in the SBI DROP bus and is configurable on a per tributary basis in the SBI ADD bus. Table 41 shows the transparent structure where "I" is used to indicate information bytes. There are two options when carrying virtual tributaries on the SBI bus, the primary difference being how the floating V5 payload is located. The first option is locked TVT mode which carries the entire VT2/TU12 virtual tributary indicated by the shaded region in Table 41. The term locked is used to indicate that the location of the V1,V2 pointer is locked. The virtual tributary must have a valid V1,V2 pointer to locate the V5 payload. In this mode the V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, are optionally generated but must be ignored by the receiving device. In locked mode timing is always sourced by the transmitting side, therefore justification requests are not used and the SAJUST_REQ signal is ignored. Other than the V1 and V2 octets which are carrying valid pointers, all octets can carry data in any format. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 41. The second option is floating TVT mode which carries the payload comprised of the V5 and I octets within the shaded region of Table 41. In this mode the V1,V2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. The V5 indicator and payload signals, SDV5, SAV5, SDPL and SAPL, must be valid and are used to locate the floating payload. The justification
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request signal can be used to control the timing on the add bus. The location of the V1,V2,V3 and V4 octets is fixed to the locations shown in Table 41. The TEMUX-84 supports both TVT modes simultaneously in the SBI DROP bus and is configurable on a per tributary basis in the SBI ADD bus.
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Table 41 Transparent VT2/TU12 Format
COL # ROW # 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 1-18 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 E1#1,1 #2,1-3,21 19 V1 I I I I I I I I V2 I I I I I I I I V3 I I I I I I I I V4 I I I I I I 20-81 V1 V2 V3 V4 82 V5 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 83-144 145 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 146-207 208 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 209-270 -
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8 9
Unused Unused
I I
-
I I
-
I I
-
I I
-
12.17 H-MVIP Data Format The H-MVIP data and Channel Associated Signaling interfaces on the TEMUX84 are able to carry all the DS0s for the T1s or all timeslots for the E1s. The E1s and T1s may be mixed on a per TUG-3/DS3 basis, so each H-MVIP signal will be carrying only E1 or T1 data. When carrying timeslots from E1s the H-MVIP frame is completely filled with 128 timeslots from four E1s but when carrying DS0s from four T1s there are not enough DS0s to completely fill the 128 byte frame. Table 42 shows how the DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame. Table 43 shows the timeslot and CAS bit H-MVIP format when in E1 mode.
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Table 42 Data and CAS T1 H-MVIP Format Timeslot Number 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 32-35 * * * 108-111 112-115 116-119 120-123 124-127 First T1 DS0 Number F-bit* 1 2 3 Undefined 4 5 6 Undefined * * * 21 Undefined 22 23 24 Second T1 DS0 Number F-bit* 1 2 3 Undefined 4 5 6 Undefined * * * 21 Undefined 22 23 24 Third T1 DS0 Number F-bit* 1 2 3 Undefined 4 5 6 Undefined * * * 21 Undefined 22 23 24 Fourth T1 DS0 Number F-bit* 1 2 3 Undefined 4 5 6 Undefined * * * 21 Undefined 22 23 24
* For applications where the F-bit value is not overwritten by the transmitter, the least significant bit of this timeslot may be carried transparently.
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Table 43 Data and CAS E1 H-MVIP Format Timeslot Number 0-3 4-7 8-11 12-15 16-19 * * * 120-123 124-127 First E1 TS Number 0 1 2 3 4 * * * 30 31 Second E1 TS Number 0 1 2 3 4 * * * 30 31 Third E1 TS Number 0 1 2 3 4 * * * 30 31 Fourth E1 TS Number 0 1 2 3 4 * * * 30 31
In the ingress direction, each CAS timeslot is encoded as follows:
1 Unused CGA 2 3 OOSMF OOF 4 A 5 B 6 C 7 D 8
The OOF bit is high when the framer has lost frame alignment. The OOSMF bit is high when E1 signaling multiframe alignment has been lost. It is also high when T1 frame alignment has been lost. The CGA bit is high if an integrated AIS or RED alarm has been declared. In the egress direction, each CAS timeslot is encoded as follows:
1 Unused 2 Unused 3 SIGC[1] 4 SIGC[0] A 5 B 6 C 7 D 8
If the INBANDCTL bit of the TPCC Configuration register is logic 1, the SIGC[1:0] field takes on the same definition as the SIGC[1:0] context bits programmed through the TPCC Indirect Channel Data registers. If INBANDCTL is logic 0, the SIGC[1:0] field is unused
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In E1 mode, the H-MVIP Common Channel Signaling interface on TEMUX-84 carries timeslot 16 for ISDN signaling, timeslot 15 and timeslot 31 for V5.2 interfaces. In T1 mode, the CCS H-MVIP interface only carries channel 28. E1 and T1 signaling may be mixed on a DS-3/TUG-3 granularity. Table 44 shows the H-MVIP format for carrying common channeling signaling and Time Slot 0 channels. These formats are fixed so when a signaling or V5.2 channel is not in use the H-MVIP timeslot is filled with all ones. Table 44 CCS and TS0 H-MVIP Format CCSID[1], CCSED[1] H-MVIP Timeslot Number 0 1 2 3 4 * * * 20 21 22 23 24 25 26 27 28 29 T1 Number (Ch 24) 1 2 3 4 5 * * * 21 22 23 24 25 26 27 28 29 30 E1 Number TS 16 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined 22 23 CCSID[2], CCSED[2] E1 Number TS 15 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined 22 23 CCSID[3], CCSED[3] E1 Number TS 31 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined 22 23 TS0ID E1 Number TS0 1 2 3 4 5 * * * 21 undefined undefined undefined undefined undefined undefined undefined 22 23
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* * * * 48 49 50 51 52 53 54 55 56 57 * * * 75 76 77 78 79 80 81 82 83 84 85 *
* * * * 49 50 51 52 53 54 55 56 57 58 * * * 76 77 78 79 80 81 82 83 84 undefined undefined *
* * * 41 42 undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined undefined *
* * * 41 42 undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined undefined *
* * * 41 42 undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined undefined *
* * * 41 42 undefined undefined undefined undefined undefined undefined undefined 43 44 * * * 62 63 undefined undefined undefined undefined undefined undefined undefined undefined undefined *
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* * 127
* * undefined
* * undefined
* * undefined
* * undefined
* * undefined
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12.18 JTAG Support The TEMUX-84 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. Figure 32 Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
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The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs. 12.18.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 33 TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
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Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
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IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out of the output, TDO, using the Shift-DR state. Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2. Figure 34 Input Observation Cell (IN_CELL)
IDCODE Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
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Figure 35 Output Cell (OUT_CELL)
Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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Figure 36 Bidirectional Cell (IO_CELL)
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 1
INPUT to internal logic
MUX
OUTPUT to pin
D C
D C
Figure 37 Layout of Output Enable and Bidirectional Cells Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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13
FUNCTIONAL TIMING
13.1 DS3 Line Side Interface Timing All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the TEMUX-84 registers are set to their default states). Figure 38 Receive Bipolar DS3 Stream
RCLK[x]
LCV
RPOS[x]
3 consec 0s
RNEG[x]
The Receive Bipolar DS3 Stream diagram (Figure 38) shows the operation of the TEMUX-84 while processing a B3ZS encoded DS3 stream on inputs RPOS and RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated corresponds to a valid B3ZS signature. A line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid B3ZS signature. Figure 39 Receive Unipolar DS3 Stream
RCLK[x] RDATI[x] RLCV[x]
X1 BIT
INFO 1
INF O 84
X2 BIT
INFO 84
C BIT
INF O 1
INFO 2
INFO 3
INFO 4
INFO 5
OR P OR M BIT
OR F BIT
LCV INDICATION
The Receive Unipolar DS3 Stream diagram (Figure 39) shows the complete DS3 receive signal on the RDAT input. Line code violation indications, detected by an upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
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Figure 40 Receive Bipolar E3 Stream
HDB3 S ignature P attern
X 0 0 V
RCLK[x] RPOS[x]
LCV 4 consec 0s 0 0 0 V B 0 0 V
RNEG[x]
The Receive Bipolar E3 Stream diagram (Figure 40) shows the operation of the TEMUX-84 while processing an HDB3-encoded E3 stream on inputs RPOS[x] and RNEG[x]. It is assumed that the first bipolar violation (on RNEG[x]) illustrated corresponds to a valid HDB3 signature. A line code violation is declared upon detection of four consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid HDB3 signature. Figure 41 Receive Unipolar E3 Stream
RCLK[x] RDATI[x] RLCV[x]
FA11
F A12
INF O X INF O X+1
INF O N INF O N+1 INF O N+2 INF O N+3 INFO N+4 INFO N+5 INFO N+6 LCV INDICATION
The Receive Unipolar E3 Stream diagram (Figure 41) shows the unipolar E3 receive signal on the RDATI[x] input. Line code violation indications, detected by an upstream HDB3 decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
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Figure 42 Transmit Bipolar DS3 Stream
TICLK[x] TCLK[x] TPO S[x] TNEG[x]
1 1 0 0 0 1 0
The Transmit Bipolar DS3 Stream diagram illustrates the generation of a bipolar DS3 stream. The B3ZS encoded DS3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a DS3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 43 Transmit Unipolar DS3 Stream
TICLK[x] TCLK[x] TDATO [x] TMFP[x]
Nib 1 Bit 4 Nib 21 Bit 1 Nib 22 Bit 4 Nib 1190 Bit 1 Nib 1 Bit 4
X1
X2
X1
The Transmit Unipolar DS3 Stream diagram (Figure 43) illustrates the unipolar DS3 stream generation. The TMFP output marks the M-frame boundary, X1 bit, in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
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Figure 44 Transmit Bipolar E3 Stream
HDB3 Signature Pattern
X 0 0 V
TICLK[x] TCLK[x] TPO S[x]
B 0 0 V
TNEG[x]
0
0
0
V
The Transmit Bipolar E3 Stream diagram (Figure 44) illustrates the generation of a bipolar E3 stream. The HDB3 encoded E3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a E3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 45 Transmit Unipolar E3 Stream TICLK[x] TCLK[x] TDATO[x] TMFP[x] The Transmit Unipolar E3 Stream diagram (Figure 45) illustrates the unipolar E3 stream generation. The TMFP output shown marks the G.832 frame boundary (the first bit of the FA1 frame alignment byte) in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
INFO X INFO X+1 FA11 FA12 FA13 INFO X+465 BIP[0] BIP[1] BIP[2] BIP[3] BIP[4] BIP[5]
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13.2 DS3 and E3 System Side Interface Timing Figure 46 Framer Mode DS3 Transmit Input Stream
TICLK[x] TDATI[x] TFPI/TMFPI[x] TFPO /TMFPO[x]
INFO 82
INFO 83
INFO 84
F4
INFO 82
IN FO 83
INFO 84
X1
IN FO 1
INFO 2
X2
IN FO 1
INFO 2
INFO 3
INFO 82
INFO 83
INFO 84
Figure 47 Framer Mode DS3 Transmit Input Stream With TGAPCLK
TICLK[x] TGAPCLK[x] TDATI[x]
INFO 83
INFO 84
INFO 1
INFO 83
INFO 84
INFO 1
INFO 2
INFO 3
INFO 1
INFO 2
INFO 3
INFO 4
INFO 81
INFO 82
INFO 83
The Framer Mode DS3 Transmit Input Stream diagram (Figure 46) shows the expected format of the inputs TDAT and TFPI/TMFPI along with TICLK and the output TFPO/TMFPO when the OPMODE_SPEx[2:0] bits are set to "DS3/E3 Framer Only mode" in the SPE Configuration registers. If the TXMFPI bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPI is valid, and the TEMUX-84 will expect TFPI to pulse for every DS3 overhead bit with alignment to TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TEMUX-84 will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the TXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPO is valid, and the TEMUX-84 will pulse TFPO once every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the TEMUX-84 will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 47. TGAPCLK remains high during the overhead bit positions.
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Figure 48 Framer Mode DS3 Receive Output Stream
RSCLK[x] RDATO [x] RFPO /RMFPO [x] RO VRHD[x]
F4 X1
INFO 1 INFO 2
INFO 82
IN FO 83
INFO 84
INFO 82
INFO 83
INFO 84
X2
INFO 1
INFO 2
INFO 3
INFO 82
INFO 83 INFO 84
Figure 49 Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK[x] RDATO[x]
INFO 82
IN FO 83
INFO 84
INFO 82
INFO 83
INFO 84
INFO 1
INFO 2
INFO 84
INFO 1
INFO 2
IN FO 3
INFO 82
INFO 83 INFO 84
The DS3/E3 Framer Only Mode Receive Output Stream diagram (Figure 48) shows the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the OPMODE_SPEx[2:0] bits are set to "DS3/E3 Framer Only mode" in the SPE Configuration registers. Figure 48 shows the data streams when the TEMUX-84 is configured for the DS3 receive format. If the RXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse high for one RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure 48), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. Figure 49 shows the output data stream with RGAPCLK in place of RSCLK when the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register set to logic 1. RGAPCLK remains high during the overhead bit positions. Figure 50 Framer Mode G.751 E3 Transmit Input Stream
TICLK[x] TDATI[x] TFPI/TMFPI[x] TFPO/TMFPO[x]
1 1 1 1 0 1 0 0 0 0 RAI N at
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
bit13
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Figure 51 Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK
TICLK[x] TG APCLK[x] TDATI[x]
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
bit13
bit14
The Framer Mode G.751 E3 Transmit Input Stream diagrams (Figure 50 and Figure 51) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the TEMUX-84 is configured for the E3 G.751 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the frame alignment signal in the G.751 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 1536 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 51. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK. Figure 52 Framer Mode G.751 E3 Receive Output Stream
RSCLK[x] RDATO[x] RFPO/RMFPO[x] ROVRHD[x]
1 1 1 1 0 1 0 0
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
0
0
RA I
N at
bit13
Figure 53 Framer Mode G.751 E3 Receive Output Stream with RGAPCLK
RG APCLK[x] RDATO[x]
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
bit13
The Framer Mode G.751 E3 Receive Output Stream diagrams (Figure 52 and Figure 53) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the TEMUX-84 is configured for the E3 G.751 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the framing alignment signal in the G.751 E3 output data
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stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. If the PYLD&JUST register bit in the E3 FRMR Maintenance Options register is set to logic 0, the Cjk and Pk bits in the RDATO stream will be marked as overhead bits. If the PYLD&JUST register bit is set to logic 1, the Cjk and Pk bits in the RDATO stream will be marked as payload. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 53. Figure 54 Framer Mode G.832 E3 Transmit Input Stream
TICLK[x] TDATI[x] TFPI/TMFPI[x] TFPO /TM FPO [x]
FA1 1 FA1 2 FA1 3 FA1 4 FA1 5 FA1 6 FA1 7 FA1 8
Oct 530 1 O ct 530 2 Oct 530 3 Oct 530 4 O ct 530 5 Oct 530 6 O ct 530 7 Oct 5308
Oct N 1
O ct N 2
O ct N 3
Figure 55 Framer Mode G.832 E3 Transmit Input Stream With TGAPCLK
TICLK[x] TGAPCLK[x] TDATI[x]
O ct 530 1 Oct 530 2 Oct 530 3 Oct 5304 O ct 530 5 Oct 5306 O ct 5307 O ct 530 8
Oct N 1
O ct N 2
Oct N 3
The Framer Mode G.832 E3 Transmit Input Stream diagrams (Figure 54 and Figure 55) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the TEMUX-84 is configured for the E3 G.832 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 4296 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 55. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK.
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Figure 56 Framer Mode G.832 E3 Receive Output Stream
RSCLK[x] RDATO[x] RFPO /RM FPO[x] ROVRHD[x]
FA1 1 FA1 2 FA1 3 FA1 4 FA1 5 FA1 6 FA1 7 FA1 8
Oct 530 1 Oct 530 2 O ct 530 3 Oct 530 4 O ct 530 5 Oct 530 6 O ct 530 7 Oct 530 8
FA2 8
Oct 1 1
Oct 1 2
Figure 57 Framer Mode G.832 E3 Receive Output Stream with RGAPCLK
RGAPCLK[x] RDATO[x]
Oct 5301 O ct 530 2 Oct 530 3 Oct 5304 O ct 530 5 Oct 5306 O ct 530 7
O ct 530 8
Oct 1 1
O ct 1 2
The Framer Mode G.832 E3 Receive Output Stream diagrams (Figure 56 and Figure 57) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the TEMUX-84 is configured for the E3 G.832 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 output data stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in DS3 and E3 Master Unchannelized Interface Options register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 57. 13.3 Telecom DROP Bus Interface Timing Figure 58 shows the function of the various telecom DROP bus signals in AU3 mode. Data on LDDATA[7:0] is sampled on the rising edge of LREFCLK. The bytes forming the three STS-1 synchronous payload envelopes are identified when the LDPL signal is high. In this diagram, a negative stuff event is shown occurring on STS-1 #2 and a positive stuff event on STS-1 #3. The LDC1J1V1 signal pulses high, while LDPL is set low, to mark the C1 byte of the first STS-1 in every frame of the STS-3 transport envelope. The LDC1J1V1 signal is high when the LDPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The bytes forming the various tributary synchronous payload envelopes are identified by the LDTPL when set high. The LDV5 signal pulses high to mark the V5 bytes of each tributary. LDTPL and LDV5 are invalid when LDPL is set low. The three STS-1 SPEs can each have different alignments to the STS-3
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transport envelope and the alignment is changing for two of the STS-1 SPEs (STS-1 #2 and #3) due to the pointer justification events shown. Figure 58 Telecom DROP Bus Timing - STS-1 SPEs / AU3 VCs
LREFCLK LDC1J1 **** LDPL LDV5 LDTPL LDDATA[7:0]
INVALID INVALID IV IV
INVALID
INVALID
IV
IV
A1 A1 A1 A2 A2 A2 C1 C1 C1 J1 C2 H4 Vx
H1 H1 H1 H2 H2 H2 H3 H4 H3 G1
V5
STS-1 #1 SPE J1 byte Last H4 byte in tributary multiframe Any V1 - V4 byte TU#1, STS-1 #1
Negative stuff for STS-1 #2 SPE which happens to carry a non-final H4 byte Positive stuff for STS-1 #3 SPE V5 byte as marked by OTV5
The LDV5 and LDTPL signals are optional when using the ingress VTPP within the TEMUX-84 which will regenerate the LDV5 and LDTPL signals from LDC1J1V1, LDPL and the pointers within LDDATA[7:0]. In order to bypass the ingress VTPP, the data on the Telecom drop bus must be locked such that all three STS-1 SPEs are aligned to the STS-3 transport envelope with the J1 bytes immediately following the C1 bytes. This is shown in Figure 59.
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Figure 59 Telecom DROP Bus Timing - Locked STS-1 SPEs / AU3 VCs
LREFCLK LDC1J1 LDPL LDV5 LDTPL LDDATA[7:0]
A2 C1 C1 C1 J1 J1 J1 V1 V1 V1 V1 V1 V1 V1 H1 H1 H1 H2 H2 H2 H3 H3 H3 J2 V5
****
Implicit location of STS-1 SPE J1 bytes V1 byte VT #1, STS-1 #1 V1 byte VT #1, STS-1 #2 V1 byte VT #1, STS-1 #3
No stuff events possible J2 byte VT #1, STS-1 #1 V5 byte VT #1, STS-1 #2 V1 bytes VT #2
Figure 60 shows the function of the various telecom DROP bus signals in AU4 mode. Data on LDDATA [7:0] is sampled on the rising edge of LREFCLK. The bytes forming the VC4 virtual container are identified by the setting the LDPL signal high. The LDC1J1V1 signal pulses high, while LDPL is set low, to mark the single C1 byte in every frame of the AU4 transport envelope. The LDC1J1V1 signal is set high again with LDPL high to mark the J1 byte of the VC4. The bytes forming the various tributary synchronous payload envelopes are identified by the LDTPL signal being set high. The LDV5 signal pulses high to mark the V5 bytes of each outgoing tributaries.
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Figure 60 Telecom DROP Bus Timing - AU4 VC
LREFCLK LDC1J1 **** LDPL LDV5 LDT PL LDDATA [7:0]
INVALID
INVALID
A1 A2 A2 A2 C1 X X
V5
Z7
J1
NP NP NP
V1 V1 V1
National bytes V5 byte TUG3 #1 Z7 byte TUG3 #1
J1 byte VC 4 First NPI byte TUG3 #1 V1 byte TU #1, TUG2 #1, TUG3 #1
The LDV5 and LDTPL signals are optional when using the ingress VTPP within the TEMUX-84 which will regenerate the LDV5 and LDTPL signals from LDC1J1V1, LDPL and the pointers within LDDATA[7:0]. In order to bypass the ingress VTPP, the position of the single J1 byte and the VC4 is implicitly defined by the C1 byte position. In the locked AU4 mode, the VC4 is defined to be aligned to the AU4 transport envelope such that the J1 byte occupies the first available payload byte after the C1 byte, and no pointer justifications are possible. 13.4 Telecom ADD Bus Interface Timing Figure 61 shows the function of the telecom ADD bus signals in AU3 mode. Data on LADATA[7:0] is updated on the rising edge of LREFCLK. The LAC1 input is sampled on the rising edge of LREFCLK and aligns all devices on the ADD bus by marking the first C1 byte of the first STS-1 in every fourth STS-3 transport envelope. LAC1 pulses every fourth STS-3 to indicate tributary multiframe alignment on the ADD bus. The bytes forming the three STS-1 synchronous payload envelopes are identified when the LAPL signal is high. The LAC1J1V1 signal pulses high, while LAPL is set low, to mark the C1 byte of the first STS-1 in every frame of the STS-3 transport envelope. The LAC1J1V1 signal is high when the LAPL signal is high to mark every J1 byte of each of the three STS-1 SPEs. The LAV5 signal pulses high to mark the V5 bytes of each tributary. LATPL, multiplexed with LAOE shown separately in Figure 61, indicates valid tributary payload when high. During the V3 location LATPL indicates a negative pointer justification when high and during the byte after the V3 location LATPL
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low indicates a positive pointer justification. The three STS-1 SPEs have an alignment determined by the SONET/SDH Transmit Pointer Configuration registers. A pointer of 522 decimal is illustrated in Figure 61. The LAC1 signal is updated on the rising edge of LREFCLK. It is output during when the TEMUX-84 is outputing valid tributary data onto the ADD bus. It is asserted high for all bytes making up a tributary and is asserted low during overhead bytes. Figure 61 Telecom ADD Bus Timing - Locked STS-1 SPEs / AU3 VCs
LREFCLK LAC1 LAOE ****
LAC1J1V1 LAPL LAV5 LATPL LADATA[7:0]
A2 C1 C1 C1 J1 J1 J1 V1 V1 V1 V1 V1 V1 V1 H1 H1 H1 H2 H2 H2 H3 H3 H3 J2 V5
Implicit location of STS-1 SPE J1 bytes V1 byte VT #1, STS-1 #1 V1 byte VT #1, STS-1 #2 V1 byte VT #1, STS-1 #3
No stuff events possible J2 byte VT #1, STS-1 #1 V5 byte VT #1, STS-1 #2 V1 bytes VT #2
Figure 62 shows the function of the TEMUX-84 telecom ADD bus when operating in AU4 mode. In AU4 mode, the position of the single J1 byte and the VC4 is implicitly defined by the LAC1 byte position. The VC4 is defined to be aligned to the AU4 transport envelope such that the J1 byte occupies the first available payload byte after the C1 byte. No pointer justification events take place on the ADD bus. LAC1J1V1 pulses high to mark the first C1 byte, the J1 byte and the third byte after J1 of the first tributary in the AU4 stream. LAPL identifies the payload bytes on LADATA[7:0].
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Figure 62 Telecom ADD Bus Timing - Locked AU4 VC Case
LREFCLK LAC1 **** LAOE LAC1J1V1 LAPL LAV5 LADATA[7:0]
A2 C1 X X J1 R R R R R R V1 H4 R R R R R R V5 Z6
National bytes Implicit location of VC4 J1 byte First R column of TUG3 #1 V1 byte TU #1, TUG2 #1, TUG3 #1
Last H4 byte in tributary multiframe
Fixed Stuff Columns V5 byte TU #1, TUG2 #1, TUG3 #1 Z6 byte TU #1, TUG2 #1, TUG3 #3
13.4.1 Notes on 77.76 MHz Telecom Bus Operation Telecom bus operation at 77.76MHz is simply a byte interleaved multiplex of a 19.44 MByte/s stream with idle cycles. The STM-1 of interest is identified by the LSTM[1:0] bits of the Master Bus Configuration register. On the Drop bus, the three unused STM-1s are simply ignored, including parity. On the Add bus, the unused STM-1s are high-impedance by default, but the bus may be configured to drive continuously. The following is of special note: (1) Regardless of the state of the LSTM[1:0] bits, the LAC1 input pulse always identifies the first of the twelve C1 bytes. (2) The LAC1J1V1 output is only valid if the LSTM[1:0] bit are "00". The C1 indication will identify the first of the twelve C1 bytes. The J1 will be high during either the first J1 byte or the first three J1 bytes depending on whether AU3 or AU4 mode is programmed. The same is true of the V1 pulse. If more than one device is driving the bus, all devices must use the same transmit payload pointer.
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(3) Up to four devices may be directly connected to the same bus. Current consumption is minimized if all devices are the same (ie. all TEMUX-84s). All devices must receive the same LAC1 signal. (4) The INCLDC1J1V1 register bit may only be set if the LSTM[1:0] bit are "00". (5) The Telecom bus becomes unconditionally high-impedance upon either a hardware or software reset. All necessary configuration and at least one LAC1 pulse should precede the setting of the LADDOE or LAOE register bits. 13.5 SONET/SDH Serial Alarm Port Timing The timing relationships of the signals related to the remote serial alarm port are shown in Figure 63. The remote serial alarm port clocks, RADEASTCK and RADWESTCK, are nominally 9.72 MHz clocks but can range from 1.344 MHz to 10 MHz. The remote serial alarm port frame pulses, RADEASTFP and RADWESTFP, mark the first BIP-2 error bit (B1 in Figure 63) of the first tributary (TU #1 of TUG2 #1, TUG3 #1) on RADEAST and RADWEST, respectively. The frame pulses must be set high to mark every first BIP-2 error bit of the first tributary. Tributaries on RADEAST and RADWEST are arranged in the order of transmission of an STM-1 stream as defined in the references. I.e., TU #1 of TUG2 #1 in TUG3 #1, TU#1 of TUG2 #1 in TUG3 #2, TU#1 of TUG2 #1 in TUG3 #3, TU#1 of TUG2 #2 in TUG3 #1, ... TU #1 of TUG2 #7 in TUG3 #3, TU #2 of TUG2 #1 in TUG3 #1, ... TU #2 of TUG2 #7 in TUG3 #3, TU #3 of TUG2 #1 in TUG3 #1, ... TU #4 of TUG2 #7 in TUG3 #3. Timeslot assignment on RADEAST and RADWEST is unrelated to the configuration of the TUG2. Timeslots are always reserved for four tributaries in every TUG2 even if it is configured for tributaries with higher bandwidth than TU11, such as TU12. At timeslots devoted to non-existent tributaries, for example, tributary 4 of a TUG2 configured for TU12, RADEAST and RADWEST will be ignored. Each tributary in the remote serial alarm port is allocated eight timeslots. The first two timeslots, labeled B1 and B2 in Figure 63, reports the two possible BIP-2 errors in the tributary payload frame. An alarm contributing to remote defect indications is reported in the third timeslot and is labeled D in Figure 63. The timeslot labeled F report alarms contributing to remote failure indications. In extended RDI mode, the D and F bits are considered as two bit codepoint and will be reported on the RDI and RFI signals. Out of extended RDI mode, the D and F bits are independent. The remaining four timeslots are unused and are ignored.
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Figure 63 Remote Serial Alarm Port Timing
RADEASTCK/ RADWESTCK
TU #1, TUG 2 #1 X TU #1 , TUG 2 #2 TUG2 #3 TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 TUG3 #1 #2 #3 #1 #2 #3 #1 #2
...
TUG2 #6
TU #4, TUG 2 #7 X
TUG3 TUG3 TUG3 TUG3 TUG3 #2 #3 #1 #2 #3
RADEASTFP/ RADWESTFP RADEASTCK/ RADWESTCK RADEASTFP/ RADWESTFP
TU #1, TUG2 #1, TUG3 #1 TU #1, TUG2 #1, TUG3 #2
X B1 B2 D F X X X
TU #1, T UG2 #1, TUG3 #3
X B1 B2 D F X X X
TU #1, TUG2 #2, TUG3 #1
X B1 B2 D F X X X
RADEAST/ RADWEST
X B1 B2 D
F
X
X
X
13.6 SBI DROP Bus Interface Timing Figure 64 SBI DROP Bus T1/E1 Functional Timing
SREFCLK SC1FP SDDATA[7:0] SDPL SDV5 SDDP C1
*** *** *** *** *** ***
V3
V3
V3 DS0#4. V5 DS0#9.
Figure 64 illustrates the operation of the SBI DROP Bus, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting SDPL high during the V3 octet. The timing diagram also shows the location of one of the tributaries by asserting SDV5 high during the V5 octet.
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Figure 65 SBI DROP Bus DS3/E3 Functional Timing
SREFCLK SC1FP SDDATA[7:0 ] SDPL SDV5 SDDP C1
*** *** *** *** *** ***
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3 DS-3 #1
Figure 65 shows three DS-3 tributaries mapped onto the SBI bus. A negative justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3 which has SDPL asserted low. E3 is transported by the same mechanism. 13.7 SBI ADD Bus Interface Timing The SBI ADD bus functional timing for the transfer of tributaries whether T1/E1 or DS3 is the same as for the SBI DROP bus. The only difference is that the SBI ADD bus has one additional signal: the SAJUST_REQ output. The SAJUST_REQ signal is used to by the TEMUX-84 in SBI master timing mode to provide transmit timing to SBI link layer devices. Figure 66 SBI ADD Bus Justification Request Functional Timing
SREFCLK SC1FP SADATA[7:0] SAPL SAV5 SADP SAJUST_REQ C1
*** *** *** *** *** *** ***
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 66 illustrates the operation of the SBI ADD Bus, using positive and negative justification requests as an example. (The responses to the justification requests would take effect during the next multi-frame.) The negative justification request occurs on the DS-3#3 tributary when SAJUST_REQ is asserted high during the H3 octet. The positive justification occurs on the DS-3#2 tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after the H3 octet. 13.7.1 Notes on 77.76 MHz SBI Bus Operation SBI bus operation at 77.76MHz is simply a byte interleaved multiplex of a 19.44 MByte/s stream with idle cycles. The STM-1 of interest is identified by the LSTM[1:0] bits of the Master Bus Configuration register. On the Add bus, the three unused STM-1s are simply ignored, including parity. On the Drop bus, the unused STM-1s are high-impedance. The following is of special note: (1) Regardless of the state of the SSTM[1:0] bits, the SAC1FP and SDC1FP pulses always identify the first byte of the frame. (2) Up to four devices may be directly connected to the same bus. Current consumption is minimized if all devices are the same (ie. all TEMUX-84s). All devices must receive the same SAC1FP and SDC1FP signals. (3) The Telecom bus becomes unconditionally high-impedance upon either a hardware or software reset. All necessary configuration and at least one SDC1FP pulse should precede the setting of the GSOE register bit. 13.8 Egress H-MVIP Link Timing The timing relationship of the common H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVED[x], CASED[x] or CCSED, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 67. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s H-MVIP operation. The TEMUX-84 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TEMUX84 samples the data provided on MVED[x], CASED[x] and CCSED at the 3/4 point of the data bit using the rising edge of CMV8MCLK as indicated for bit 1 (B1) of time-slot 1 (TS 1) in Figure 67. B1 is the most significant bit and B8 is the least significant bit of each octet.
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Figure 67 Egress 8.192 Mbit/s H-MVIP Link Timing
CMV8MCLK (16 MHz) CMVFPC (4 MHz)
CMVFPB MVED[x] CASED[x] CCSED
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
13.9 Ingress H-MVIP Link Timing The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVID[x], CASID[x] or CCSID, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbit/s H-MVIP operation with a type 0 frame pulse is shown in Figure 68. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbit/s H-MVIP operation. The TEMUX-84 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TEMUX84 updates the data provided on MVID[x], CASID[x] and CCSID on every second falling edge of CMV8MCLK as indicated for bit 2 (B2) of time-slot 1 (TS 1) in Figure 68. The first bit of the next frame is updated on MVID[x], CASID[x] and CCSID on the falling CMV8MCLK clock edge for which CMVFPB is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet. Figure 68 Ingress 8.192 Mbit/s H-MVIP Link Timing
CMV8MCLK (16 MHz) CMVFPC (4 MHz)
CMVFPB MVID[x] CASID[x] CCSID TS0ID
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
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14
ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 45 Absolute Maximum Ratings Parameter Case Temperature under Bias Storage Temperature Supply Voltage Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature Notes on Power Supplies: 1. VDD3.3 should power up before VDD1.8. 2. VDD3.3 should not be allowed to drop below the VDD1.8 voltage level except when VDD1.8 is not powered. TJ IIN TST VDD1.8 VDD3.3 VIN Symbol Value -40 to +85 -40 to +125 -0.3 to + 3.6 -0.3 to + 5.5 -0.3 to 5.5 1000 100 20 +230 +150 Units C C VDC VDC VDC V mA mA C C
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15
D.C. CHARACTERISTICS TA = -40C to +85C, VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8% (Typical Conditions: TA = 25C, VDD3.3 = 3.3V, VDD1.8 = 1.8V) Table 46 D.C. Characteristics
Symbol Parameter Min Typ Max Units Conditions
VDD3.3 VDD1.8 VIL VIH VOL
Power Supply Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage
2.97 1.65 0 2.0 0
3.3 1.8
3.63 1.95 0.8
Volts Volts Volts Volts Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -4mA for D[7:0], LAOE, RECVCLK1, RECVCLK2, RECVCLK3, MVID[7:0], CASID[7:0], CCSID, TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATAO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, IOL = -8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SDC1FP, LAC1J1V1, LADATA[7:0], LADP, LAPL, IOL = -2mA for others. Note 3
0.1
0.4
Volts
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Symbol
Parameter
Min
Typ
Max
Units
Conditions
VOH
Output or Bidirectional High Voltage
2.4
VDD3. 3
Volts
VDD = min, IOH = -4mA for D[7:0], LAOE, RECVCLK1, RECVCLK2, RECVCLK3, MVID[7:0], CASID[7:0], CCSID, TCLK, TPOS/TDAT, TNEG/TMFP, RGAPCLK/RSCLK, RDATAO, RFPO/RMFPO, ROVRHD, TFPO/TMFPO/TGAPCLK, SBIACT, IOH = -8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SDC1FP, LAC1J1V1, LADATA[7:0], LADP, LAPL, IOH = -2mA for others. Note 3
VT+
Reset Input High Voltage
2.0
Volts
TTL Schmidt
VT-
Reset Input Low Voltage
0.8
Volts
VTH
Reset Input Hysteresis Voltage
TBD
Volts
IILPU IIHPU IIL IIH CIN
Input Low Current Input High Current Input Low Current Input High Current Input Capacitance
+20 -10 -10 -10 5
+100 +10 +10 +10
A A A A pF
VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF
COUT
Output Capacitance
5
pF
Excluding Package, Package Typically 2 pF
CIO
Bidirectional Capacitance
5
pF
Excluding Package, Package Typically 2 pF
IDDOP1
Operating Current
340 5
500
mA
VDD1.8 = 1.94 V VDD3.3 = 3.56 V Outputs Unloaded, Telecom to SBI mode
IDDOP2
Operating Current
340 5
500
mA
VDD1.8 = 1.94 V VDD3.3 = 3.56 V Outputs Unloaded, DS3 to MVIP mode
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Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
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MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8%) Table 47 Microprocessor Interface Read Access Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state Min 10 5 10 10 20 0 5 30 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 42 Microprocessor Interface Read Timing tSAR A[12:0] tS ALR tVL ALE tSLR (CSB+RDB) tZ INTH INTB tHLR tHALR
Valid
Address
tH AR
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable.
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5. Parameter tHAR is not applicable if address latching is used. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Table 48 Microprocessor Interface Write Access Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 20 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 43 Microprocessor Interface Write Timing
A[12:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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TEMUX-84 TIMING CHARACTERISTICS (TA = -40C to +85C VDD3.3 = 3.3V 8%, VDD1.8 = 1.8V 8%) Table 49 RSTB Timing Symbol tVRSTB Description RSTB Pulse Width Min 100 Max Units ns
Figure 44 RSTB Timing
HDB3 Signature Pattern
X 0 0 V
TICLK[x] TCLK[x] TPO S[x]
B 0 0 V
TNEG[x]
0
0
0
V
Table 50 DS3/E3 Transmit Interface Timing Symbol fTICLK t0TICLK t1TICLK tSTFPI Description TICLK[3:1] Frequency TICLK[3:1] minimum pulse width low TICLK[3:1] minimum pulse width high TFPI/TMFPI[x] to TICLK[x] Set-up Time (LOOPT=0, active TICLK edge set by TDATIFALL bit) TFPI/TMFPI[x] to RCLK[x] Set-up Time (LOOPT=1) tHTFPI TFPI/TMFPI[x] to TICLK[x] Hold Time (LOOPT 0 ti TICLK d tb
273
Min
Max Units 52 MHz ns ns ns
7.7 7.7 5
5 1 ns
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(LOOPT=0, active TICLK edge set by TDATIFALL bit) TFPI/TMFPI[x] to RCLK[x] Hold Time (LOOPT=1) tSTDATI TDATI[x] to TICLK[x] Set-up Time (LOOPT = 0, active TICLK edge set by TDATIFALL bit) TDATI[x] to RCLK[x] Set-up Time (LOOPT = 1) tHTDATI TDATI[x] to TICLK[x] Hold Time (LOOPT = 0, active TICLK edge set by TDATIFALL bit) TDATI[x] to RCLK[x] Hold Time (LOOPT = 1) tPTGAP tPTFPO TICLK[x] to TGAPCLK[x] Prop Delay (LOOPT = 0) RCLK[x] to TGAPCLK[x] Prop Delay (LOOPT = 1) TICLK[x] to TFPO/TMFPO[x] Prop Delay (LOOPT = 0, active TICLK edge set by TDATIFALL bit) RCLK[x] to TFPO/TMFPO[x] Prop Delay (LOOPT = 1) tSTGAP tHTGAP tPTCLK tPTPOS tPTNEG tPTPOS2 tPTNEG2 TDATI[x] to TGAPCLK[x] Set-up Time TDATI[x] to TGAPCLK[x] Hold Time TICLK[x] Edge to TCLK[x] Edge Prop Delay TCLK[x] Edge to TPOS/TDAT[x] Prop Delay TCLK[x] Edge to TNEG/TMFP[x] Prop Delay TICLK[x] High to TPOS/TDAT[x] Prop Delay TICLK[x] High to TNEG/TMFP[x] Prop Delay 1 5 ns
5 1 ns
1 2 2 2 10 10 12 ns ns
2 2 2 2 -1 -1 2 2
12 ns ns 13 4 4 13 13 ns ns ns ns ns
Note: The "[x]" implies the parameters for a data signal are only in relation to the associated clock.
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Figure 69 DS3/E3 Transmit Interface Timing TICLK/RCLK tS TFPI TFPI/TMFPI tH TFPI
TICLK/RCLK tS TDATI TDATI tH TDATI
TICLK/RCLK tPTFPO TFPO/TMFPO
TICLK/RCLK tPTGAP TGAPCLK tPTGAP
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TGAPCLK tS TGAP TDATI
TICLK=0, TRISE=0 TICLK=0, TRISE=1
tH TGAP
TICLK
TICLK
TCLK
TCLK
t TPOS P
TPOS/TDAT TPOS/TDAT
t TPOS P
t TNEG P
TNEG/TMFP TNEG/TMFP
t TNEG P
TICLK=1, TRISE=X
TICLK
t TCLK tTCLK P P
TCLK
t TPOS2 P
TPOS/TDAT
t TNEG2 P
TNEG/TMFP
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Table 51 DS3/E3 Receive Interface Timing Symbol fRCLK t0RCLK t1RCLK tSRPOS tHRPOS tSRNEG tHRNEG tPRDATO tPRFPO tPROVRHD tPRGAP Description RCLK[3:1] Frequency RCLK[3:1] minimum pulse width low RCLK[3:1] minimum pulse width high RPOS/RDAT[x] Set-up Time RPOS/RDAT[x] Hold Time RNEG/RLCV[x] Set-Up Time RNEG/RLCV[x] Hold Time RSCLK[x] Edge to RDATO[x] Prop Delay RSCLK[x] Edge to RFPO/RMFPO[x] Prop Delay RSCLK[x] Edge to ROVRHD[x] Prop Delay RGAPCLK[x] Edge to RDATO[x] Prop Delay 7.7 7.7 4 1 4 1 -2 -2 -2 -2 2 2 2 2 Min Max Units 52 MHz ns ns ns ns ns ns ns ns ns ns
Figure 70 DS3/E3 Receive Interface Timing RCLK tS RPOS RPOS/RDAT tS RNEG RNEG/RLCV tH RNEG tH RPOS
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RSCLK tP RDATO RDATO tP RFPO RFPO/RMFPO tPROVRHD ROVRHD Dashed line RSCLK represents behaviour when RSCLKR register bit = 1. RGAPCLK tP RGAP RDATO Dashed line RSCLK represents behaviour when RSCLKR register bit = 1.
Notes on DS3/E3 Interface Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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2.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs.
3. 4.
Table 52 Line Side Telecom Bus Input Timing - 19.44 MHz (Figure 74) Symbol Description LREFCLK Frequency LREFCLK Duty Cycle LREFCLK skew relative to SREFCLK CLK52M Frequency (51.84 MHz) CLK52M Frequency (44.928 MHz) CLK52M Duty Cycle tSTEL THTEL Min 19.44 -50 ppm 40 -10 51.84 -50 ppm 44.928 -50 ppm 40 Max 19.44 +50 ppm 60 10 51.84 +50 ppm 44.928 +50 ppm 60 Units MHz % ns MHz MHz % ns ns
All Telecom BUS Inputs Set-Up Time 5 to LREFCLK All Telecom BUS Inputs Hold Time to LREFCLK 1
Line Side Telecom Bus Input Timing - 77.76 MHz (Figure 74) Symbol Description LREFCLK Frequency LREFCLK Duty Cycle LREFCLK skew relative to SREFCLK Min 77.76 -50 ppm 40 -5 Max 77.76 +50 ppm 60 5 Units MHz % ns
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Symbol
Description CLK52M Frequency (51.84 MHz) CLK52M Frequency (44.928 MHz) CLK52M Duty Cycle
Min 51.84 -50 ppm 44.928 -50 ppm 40
Max 51.84 +50 ppm 44.928 +50 ppm 60
Units MHz MHz % ns ns
tSTEL THTEL
All Telecom BUS Inputs Set-Up Time 3 to LREFCLK All Telecom BUS Inputs Hold Time to LREFCLK 0
Notes on Telecom Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. Figure 71 Line Side Telecom BUS Input Timing
LREFCLK tS TEL tH TEL
LAC1, LDDATA[7:0] LDDP,LDPL LDV5,LDC1J1, LDTPL, LDAIS
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Table 53 Telecom Bus Output Timing - 19.44 MHz (Figure 72 and Figure 73) Symbol tPTEL tZTEL tPTELOE Description LREFCLK rising to all Telecom BUS Outputs Valid LREFCLK rising to all Telecom BUS tristateable Outputs going tristate LREFCLK rising to all Telecom BUS tristateable Outputs going valid from tristate Min 3 3 0 Max 20 20 13 Units ns ns ns
Table 54 Telecom Bus Output Timing - 77.76 MHz (Figure 72 and Figure 73) Symbol tPTEL tZTEL tPTELOE Description LREFCLK rising to all Telecom BUS Outputs Valid LREFCLK rising to all Telecom BUS tristateable Outputs going tristate LREFCLK rising to all Telecom BUS tristateable Outputs going valid from tristate Min 1 1 1 Max 7 7 7 Units ns ns ns
Notes on Telecom Bus Output Timing: 1. 2. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. The propagation delay, tPTEL, should be used when Telecom bus outputs are always driven as configured by LADDOE in register. The propagation delays, tPTELOE and tZTEL, should be used when the Telecom bus outputs are multiplexed with other TEMUX-84 devices using the tristate capability of
4.
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the outputs as configured by LADDOE in register. Note that under any specific operating condition, tZTEL is guaranteed to be less than tPTELOE. Figure 72 Telecom BUS Output Timing
LREFCLK tPTEL
LADATA[7:0] LADP, LAPL LAV5,LAOE LAC1J1V1
Figure 73 Telecom BUS Tristate Output Timing
LREFCLK tPTELOE LADATA[7:0] LADP, LAPL LAV5 tZ TEL
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Table 55 SBI ADD BUS Timing - 19.44 MHz (Figure 74) Symbol Description SREFCLK Frequency SREFCLK Duty Cycle tSSBIADD tHSBIADD tPSBIADD tZSBIADD All SBI ADD BUS Inputs Set-Up Time to SREFCLK All SBI ADD BUS Inputs Hold Time to SREFCLK SREFCLK to SAJUST_REQ Valid SREFCLK to SAJUST_REQ Tristate Min 19.44 -50 ppm 40 4 0 2 2 15 15 Max 19.44 +50 ppm 60 Units MHz % ns ns ns ns
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Table 56 SBI ADD BUS Timing - 77.76 MHz (Figure 74) Symbol Description SREFCLK Frequency SREFCLK Duty Cycle tSSBIADD tHSBIADD tPSBIADD tZSBIADD All SBI ADD BUS Inputs Set-Up Time to SREFCLK All SBI ADD BUS Inputs Hold Time to SREFCLK SREFCLK to SAJUST_REQ Valid SREFCLK to SAJUST_REQ Tristate Min 77.76 -50 ppm 40 3 0 1 1 6 6 Max 77.76 +50 ppm 60 Units MHz % ns ns ns ns
Notes on SBI Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. Figure 74 SBI ADD BUS Timing SREFCLK tSSBIADD tHSBIADD
SAC1FP SADATA[7:0] SADP,SAPL SAV5
tPSBIADD tZSBIADD SAJUST_REQ
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 57 SBI DROP BUS Timing - 19.44 MHz (Figure 72 and Figure 75) Symbol tSSBIDROP tHSBIDROP tPSBIDROP tZSBIDROP tPOUTEN tZOUTEN tSDET tHDET Description SDC1FP Set-Up Time to SREFCLK SDC1FP Hold Time to SREFCLK SREFCLK to All SBI DROP BUS Outputs Valid SREFCLK to All SBI DROP BUS Outputs Tristate SBIDET[1] and SBIDET[0] low to All SBI DROP BUS Outputs Valid SBIDET[1] and SBIDET[0] high to All SBI DROP BUS Outputs Tristate SBIDET[n] Set-Up Time to SREFCLK SBIDET[n] Hold Time to SREFCLK Min 4 0 2 2 0 0 4 0 15 15 12 12 Max Units ns ns ns ns ns ns ns ns
Table 58 SBI DROP BUS Timing - 77.76 MHz (Figure 75 to Figure 76) Symbol tSSBIDROP tHSBIDROP tPSBIDROP tZSBIDROP Description SDC1FP Set-Up Time to SREFCLK SDC1FP Hold Time to SREFCLK SREFCLK to All SBI DROP BUS Outputs Valid SREFCLK to All SBI DROP BUS Outputs Tristate Min 3 0 1 1 7 7 Max Units ns ns ns ns
Notes on SBI Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs.
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. Figure 75 SBI DROP BUS Timing
SREFCLK tP S BIDROP
SDC1FP SDDATA[7:0] SDDP, SDPL SDV5,SBIACT
tZ SBIDRO P SDDATA[7:0] SDDP, SDPL SDV5 tSSBIDROP SDC1FP tHSBIDRO P
Figure 76 SBI DROP BUS Collision Avoidance Timing
SREFCLK tSDET SBIDET[n] tPOUTEN SDDATA[7:0] SDDP, SDPL SDV5 tZOUTEN tHDET
PROPRIETARY AND CONFIDENTIAL
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 59 Egress Flexible Bandwidth Port Timing (Figure 77) Symbol Description EFBWCLK[n] Frequency EFBWCLK[n] High Phase EFBWCLK[n] Low Phase tSEFBW tHEFBW tPEFBW EFBWDREQ[n] Set-Up Time to EFBWCLK[n] Rising Edge EFBWDREQ[n] Hold Time to EFBWCLK[n] Rising Edge EFBWCLK[n] Falling Edge to EFBWDAT[n] and EFBWEN[n] Valid Min 0 7 7 4 0 2 15 Max 52 Units MHz ns ns ns ns ns
Figure 77 Egress Flexible Bandwidth Port Timing
EFBWCLK[n] tS EFBW tH EFBW
EFBWDREQ[n]
tP EFBW EFBWDAT[n], EFBWEN[n]
PROPRIETARY AND CONFIDENTIAL
287
PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 60 Ingress Flexible Bandwidth Port Timing (Figure 78) Symbol Description IFBWCLK[n] Frequency IFBWCLK[n] High Phase IFBWCLK[n] Low Phase tSIFBW tHIFBW IFBWDAT[n] and IFBWEN[n] Set-Up Time to IFBWCLK[n] Rising Edge IFBWDAT[n] and IFBWEN[n] Hold Time to IFBWCLK[n] Rising Edge Min 0 7 7 4 1 Max 52 Units MHz ns ns ns ns
Figure 78 Ingress Flexible Bandwidth Port Timing
IFBWCLK[n] tS IFBW IFBWDAT[n], IFBWEN[n] tH IFBW
Notes on Flexible Bandwidth Port Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 5. 6. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 61 H-MVIP Egress Timing (Figure 79) Symbol Description CMV8MCLK Frequency (See Note 3) Min 16.384 -50 pp m 40 4.092 40 -10 Max 16.384 +50 pp m 60 4.100 60 10 Units MHz
CMV8MCLK Duty Cycle CMVFPC Frequency (See Note 4) CMVFPC Duty Cycle tPMVC tSHMVED tHHMVED tSMVFPB tHMVFPB CMV8MCLK to CMVFPC skew
% MHz % ns ns ns ns ns
MVED[21:1], CASED[21:1], CCSED[3:1] 5 Set-Up Time MVED[21:1], CASED[21:1], CCSED[3:1] 5 Hold Time CMVFPB Set-Up Time CMVFPB Hold Time 5 5
Notes on H-MVIP Egress Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Measured between any two CMV8MCLK falling edges. 4. Measured between any two CMVFPC falling edges.
PROPRIETARY AND CONFIDENTIAL
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 79 H-MVIP Egress Data & Frame Pulse Timing
CMVFPC tSMVFPB CMVFPB tPMVC CMV8MCLK tSHMVED tHHMVED tHMVFPB
MVED[x] CASED[x] CCSED[x]
Table 62 H-MVIP Ingress Timing (Figure 80) Symbol tPHMVID Description CMV8MCLK Low to MVID[21:1], CASID[21:1], CCSID[3:1], TS0ID Valid Min 4 Max 25 Units ns
Notes on H-MVIP Ingress Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs. 3. Output propagation delays of signal outputs that are specified in relation to a reference output are measured with a 50 pF load on both the signal output and the reference output.
PROPRIETARY AND CONFIDENTIAL
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PRELIMINARY DATASHEET PMC-1991437 ISSUE 5
PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 80 H-MVIP Ingress Data Timing
CMV8MCLK tPHMVID MVID[x] CASID[x] CCSID[x]
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 63 XCLK Input (Figure 81) Symbol tLXCLK tHXCLK tXCLK Description XCLK_T1 and XCLK_E1 Low Pulse Width XCLK_T1 and XCLK_E1 High Pulse Width XCLK_T1 and E1_XLK Period (typically 1/37.056 MHz 32 ppm for XCLK_T1 and 1/49.152 MHz for XCLK_E1) Min 8 8 20 Max Units ns ns ns
Figure 81 XCLK Input Timing
t HXCLK
XCLK_T1 or XCLK_E1
t L XCLK
t XCLK
Table 64 Transmit Line Interface Timing (Figure 82) Symbol Description CTCLK Frequency (Must be integer multiple of 8 KHz.) tHCTCLK tLCTCLK CTCLK High Duration CTCLK Low Duration Min 0.008 60 60 Max 2.048 Units MHz ns ns
PROPRIETARY AND CONFIDENTIAL
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 82 Transmit Line Interface Timing
t HCTCLK
CTCLK
t L CTCLK
t CTCLK
Notes on Ingress and Egress Serial Interface Timing:
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps. 2. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 3. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 4. Setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. Output propagation delays are measured with a 50 pF load on all outputs with the exception of the high speed DS3/E3 outputs (TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1]). The TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1] output propagation delays are measured with a 20 pF load.
Table 65 Remote Serial Alarm Port Timing Symbol Description Min Max Units
RADEASTCK and RADWESTCK Frequency
1.344
10
MHz
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
RADEASTCK and RADWESTCK Duty Cycle tHRADFP tSRADFP
tHRAD tSRAD
40 5 5 5 5
60
% ns ns ns ns
RADEASTFP and RADWESTFP Hold Time RADEASTFP and RADWESTFP Setup Time RADEAST and RADWEST Hold Time RADEAST and RADWEST Setup Time
Figure 83 Remote Serial Alarm Port Timing
RADEASTCK/ RADWESTCK tSRADFP RADEASTFP/ RADWESTFP tSRAD RADEAST/ RADWEST tHRAD tHRADFP
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Table 66 JTAG Port Interface Symbol Description Min Max Units
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100
1 60
MHz % ns ns ns ns
50
ns ns
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 84 JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
18
ORDERING AND THERMAL INFORMATION Table 67 Ordering Information Part No. Description
PM8316-PI
324 Plastic Ball Grid Array (PBGA)
Table 68 Thermal information - Theta Ja vs. Airflow
Theta Ja (C/W) @ specified power Dense Board Convection
39.4
Forced Air (Linear Feet per Minute) 100 200 300 400 500
35.1 32.0 30.0 28.6 27.7
JEDEC Board
22.1
20.4
19.2
18.4
17.9
17.4
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
19
MECHANICAL INFORMATION Figure 85 324 Pin PBGA 23x23mm Body
0 .2 0 (4X )
D D1
A1 BALL PAD CORN ER
A
0.30 M C A B 0.10 M C B
22 21 20 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 19 11
A1 BAL L CO RNER
e
A1 BALL INDICATOR
E1
E
45 o CHAM F ER 4 PLACES
J I
A B C D E F G H J K L M N P R T U V W Y AA AB
b "d" DIA . 3 PLACES
TOP VIEW
C A
30 o TYP
BO TT OM V IEW
bb b C
aaa C
C
A1
A2
SEATING PLA NE
SIDE VIEW
NO TE S: 1) ALL D IM ENSIO NS IN M ILLIM ET ER . 2) DIM ENSION aaa DENO TE S C O PLANA RIT Y. 3) DIM ENS IO N bbb DE NO TES PAR ALLE L.
1.82 2.03 2.22
2.07 2.28 2.49
0.40 0.50 0.60
1.12 1.17 1.22 23.00
19.00 19.50 20.20
0.30 0.36 0.40
0.55 0.61 0.67 23.00
19.00 19.50 20.20 1.00 1.00
0.50 0.63 0.70 1.00 1.00 0.15 0.35
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
NOTES
PROPRIETARY AND CONFIDENTIAL
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PM8316 TEMUX-84
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1991437(P5) ref PMC-991191 (P6) Issue date: October 2001
PMC-Sierra, Inc.. .415.6000
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 _604

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